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HDL IP Importer

Import HDL IP core into SoC model

Since R2023a


Use the HDL IP Importer tool to import an existing HDL IP core into an SoC Simulink® model. The tool takes you through the steps to generate a library block that you can integrate into your Simulink model. You can then simulate, build, and deploy the model on a hardware board using the SoC Builder tool.


Use this tool only to target Xilinx® devices.

Using this tool, you can:

  • Import a Xilinx or custom HDL IP as a Simulink block.

  • Generate the editable simulation and customization files with the .m and .tcl extensions, respectively.

  • Specify the block name, library name, and library location.

  • Include multiple instances of the generated block in the same Simulink model.

  • Specify constraints on the HDL IP core.

  • Review or update the HDL IP interfaces that the tool adds as ports to the generated block.

  • Review clock and reset interfaces and select the required source for these interfaces.

  • Specify a device tree file for the HDL IP and the pre- and post-load scripts.

You can also import multiple HDL IP cores into the Simulink model as a single block. To import multiple HDL IP cores, package multiple IPs into single IP in Vivado®, and then use the HDL IP Importer tool.

The tool supports the AXI4-Stream, AXI4-Stream Video, AXI4 Master, I/O, clock, and reset HDL IP interfaces for the block generation. You can add these interfaces as ports to the generated block. The tool supports the AXI4 Slave HDL IP interface for block generation only. The tool does not add the AXI4 Slave interface to the generated block as a port.

HDL IP Importer tool, open for configuration

Open the HDL IP Importer

  • Simulink toolstrip: On the System on Chip tab, click HDL IP Importer.

  • MATLAB® command prompt: Enter hdlIPImporter.

Version History

Introduced in R2023a