Get Started with SoC Blockset (for AMD)

SoC Blockset™ (for AMD) enables you to design, simulate, deploy, and verify applications on AMD^® FPGAs and Adaptive SoCs. Using MATLAB^® and Simulink^®, the product provides hardware/software co-design workflows that target AMD devices on off-the-shelf and custom boards. You can model hardware and software applications, perform bit-accurate simulation, generate IP cores (with HDL Coder™), build embedded software (with Embedded Coder^®), and program development boards using AMD Vitis^®.

SoC Blockset (for AMD) enables HDL Coder to generate synthesizable C++ from MATLAB code for Vitis HLS and RTL from Simulink models with Vitis Model Composer blocks. You can perform hardware-in-the-loop (HIL) testing on designs deployed to development boards and verify deployed designs using MATLAB and Simulink testbenches.

The product includes reference designs for communications, vision, deep learning, and control applications for Versal^®, Zynq^® UltraScale+™ MPSoC/RFSoC, and Zynq-7000 devices, and for AMD FPGAs.

Tutorials

SoC Workflows Overview

• SoC Targeting Workflows
  Choose between IP core generation workflow and SoC modeling and generation workflow for deploying your design on an SoC device.

IP Core Generation

• Targeting FPGA and SoC Hardware Overview
  High-level steps for targeting an FPGA or SoC platform.
• Hardware-Software Co-Design Workflow for SoC Platforms
  High-level workflow steps for targeting an SoC platform.

SoC Modeling and Generation

• Use Template to Create SoC Model
  Create SoC models using Simulink project templates.
• Create an SoC Project Application
  Step-by-step instructions and guidelines for creating an SoC project and models for an SoC application.

FPGA Verification and Debug

• FPGA-in-the-Loop Verification
  Verify HDL designs on FPGA hardware using FPGA-in-the-loop simulation.
• FPGA Debug
  Debug and test FPGA designs using FPGA data capture and AXI manager features.

Featured Examples

Get Started with SoC Blockset for AMD

Get started with deploying an algorithm on an SoC hardware board.

• Since R2026a
• Open Script

Get Started with IP Core Generation from Simulink Model

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® ZC702 evaluation kit.

(HDL Coder)

Get Started with IP Core Generation from MATLAB Function

Use the MATLAB® HDL Workflow Advisor to generate a customized IP core that blinks LEDs on an FPGA board. This example deploys the generated IP core on the ZedBoard hardware, but you can use any Xilinx® Zynq® platform or Xilinx FPGA with a MicroBlaze processor.

(HDL Coder)

Streaming Data from Hardware to Software Using AMD SoC Devices

A systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC builder workflow.

• Open Script

Get Started with RFSoC Devices

Get started with modeling wireless applications and implementing them on AMD® Zynq® UltraScale+™ RFSoC devices.

• Open Live Script

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop for AMD Devices

Set up an FPGA-in-the-Loop (FIL) application.

• Open Script