Comparison of IP Core Deployment and Verification Techniques

Since R2023b

When prototyping a design on hardware, you must generate a bitstream and program your target device over multiple design iterations. Using the Simulink^® Toolstrip to generate a bitstream allows you to rapidly deploy the IP core to your target device. You can stay in the Simulink environment, while you make changes to your design, re-generate the bitstream, or program your device without having to repeat previously completed tasks.

Prior to R2023b, you completed the sequential tasks in HDL Workflow Advisor to generate an IP core project to enable the host interface script and software interface generation. Starting in R2023b, you can generate the software interface model and the host interface script from the Simulink Toolstrip directly by using the IP core editor to configure the IP Core settings and interface mapping. Use the Simulink Toolstrip to prototype your design and generate a bitstream, host interface script, and software interface model with higher flexibility, efficiency, and scalability.

Embedded System Integration Process Comparison

To compare the IP core generation processes using HDL Workflow Advisor and the Simulink Toolstrip, see Comparison of IP Core Generation Techniques. This table compares the process to generate a bitstream by using the HDL Workflow Advisor and the Simulink Toolstrip:

Workflow Advisor Task	Simulink Toolstrip Step
Open the HDL Workflow Advisor	Open the HDL Coder app from the Apps tab on the Simulink Toolstrip. In the HDL Code tab, in the Output selection, select IP Core from the drop-down button.
Task 4.1 Create Project	In the HDL Code tab, select Build Bitstream > Create IP Core Project. To specify a custom project name and other options, in the HDL Code tab, select Build Bitstream > Deployment Settings and specify the project-related settings under Create IP Project Settings.
Task 4.2 Generate Software Interface	To generate the software interface model, in the HDL Code tab, select Build Bitstream > Software Interface Model. To specify the operating system for the software model, in the HDL Code tab, select Build Bitstream > Deployment Settings, and specify the project-related settings under Generate Software Interface. You can generate the software interface model without generating the IP core. To generate the host interface script, in the HDL Code tab, select Host Interface Script > Host Interface Script. To specify the target interface for the host interface script, in the HDL Code tab, select Host Interface Script > Host target interface and select either `Ethernet` or `JTAG` from the drop-down menu options. You can generate the host interface script without generating the IP core.
Task 4.3 Build FPGA Bitstream	In the HDL Code tab, click the Build Bitstream button. To specify the options related to bitstream build, in the HDL Code tab, select Build Bitstream > Deployment Settings, and specify the bitstream-related settings under Build Bitstream Settings.
Task 4.4 Program Target Device	In the HDL Code tab, select Build Bitstream > Program Target Device. To specify the options related to the bitstream build, in the HDL Code tab, select Build Bitstream > Deployment Settings, and specify the program target device settings under Program Device Settings.

Limitations

When deploying and verifying your IP core using either the HDL Workflow Advisor or the Simulink Toolstrip:

You can specify the parameters and settings for a the embedded system integration tasks by using the HDL Workflow Advisor or you can specify the IP core deployment settings on the HDL Code tab by clicking Build Bitstream > Deployment Settings. Updating a parameter using one of these options also updates the parameter in the other locations.
When the HDL Workflow Advisor is open, you cannot perform any IP core generation, deployment, or verification actions from the Simulink Toolstrip. To use the Simulink Toolstrip to deploy and validate an IP core, first close the HDL Workflow Advisor.
When the Target Device parameter is set to a generic FPGA device, the Build Bitstream and Host Interface Script buttons are dimmed.
You cannot generate a host interface model from the Simulink Toolstrip.