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Verify the Verilog generated by HDLcoder
You can use the Generate Testbench feature of HDL Coder to generate an HDL testbench that takes the simulation input and output ...

2年弱前 | 0

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The Simulink model is fixed-point based on floating-point numbers
You can put a breakpoint in the MATLAB Function block to see whee the code is generating the double output. See this link on how...

2年弱前 | 0

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How to use the FFT block of Vitis Model Composer
"Vitis Model Composer" is a third-party blockset provided by Xilinx, so it is best to reach out to Xilinx technical support if y...

2年弱前 | 0

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Remainder of a division operation in System Generator
When you say "running value", what is the range of the update value? If the initial value can be set to the proper range of 0 to...

2年弱前 | 0

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How to read a vectore in worksapce as a signal in Simulink with variable starting index
I suggest using the MATLAB Function block for the index calculation. You can use the initial index and then compute the new inde...

2年弱前 | 0

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Blocks for HDL Code generation
If you type hdllib on at the MATLAB command line, the Simulink library browser will show you the list of blocks supported for HD...

2年弱前 | 1

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Display images on video viewer in simulink in for loop
It would help to have a sample model (a simple one showing the problem will suffice). If you wish to view the intermediate resu...

約2年前 | 0

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Atan2 block native floating point single HDL generation needs more pipelining
I am glad that using the Complex to Magnitude Angle block worked out for you. Adding that option as an answer in case others run...

2年以上前 | 0

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how to implement this function in fixed point and generate the hdl code for the function?
For HDL, you will need to implement this in a streaming fashion. lease take a look at the FFT Streaming model provided in this e...

2年以上前 | 0

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Parallelise data coming out of RAM Simulink
What kind of processing do you want to do on the 512-element array? For an HDL implementation, it makes sense to work on a singl...

2年以上前 | 0

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Downsampling using MATLAB Simulink for an input signal
You can use the Downsample block with Scalar input in DSP System Toolbox. As Walter points out, you can also use the HDL Optimi...

2年以上前 | 0

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signal over lapping in Down sampler output for ZYNQ FPGA
Are you trying to implement a chaneelizer? If so, here is the behavioral version in DSP System Toolbox and its HDL equivalent.

2年以上前 | 0

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difference in column based and element based decimated output of a down sampler
Muhammad, I assume that you are doing this as a multirate system in the FPGA. To mimic that behavior, send in scalar input to th...

2年以上前 | 0

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Difference in the output of CIC decimator while using with unbuffer and without unbuffer
Could you please provide a model that shows this behavior (you may want to try it using a fixed known input first)? Are you sen...

2年以上前 | 0

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How do I generate HDL Code for my model that has frame based communication in Simulink HDL Coder 2.1 (R2011a)?
I have one clarification on your question. When you say "frame based communication" - are you referring to processing multiple s...

2年以上前 | 0

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Different CIC decimator Response in normal simulation and FPGA implementation
It would be helpful to see your model - are you using the CIC Decimation block? Did you build your own? Have you tired using the...

2年以上前 | 0

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Vision HDL Toolbox Support - available inputs
Currently, the only way to do it live with the Vision HDL Toolbox Support Package for Xilinx Zynq is with the FMC + HDMI camera....

2年以上前 | 0

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Error message "Found unsupported dimensions on matrix type at input port: 0" has occurred while generating HDL(Verilog) Code from matlab algorithm.
It would be helpful to see the code (at least at the high level of the testbench and top level design). For conversion to HDL, y...

2年以上前 | 0

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Xilinx System Generator error with storage container type
Hi George, Xilinx System Generator is not a MathWorks product. I recommend reaching out directly to Xilinx for troubleshooting ...

2年以上前 | 0

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Vision HDL Toolbox Support - available inputs
You can capture the video onto your computer and use the Vision HDL Toolbox model with a video source. This is shown in this Vi...

2年以上前 | 0

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How to generate verilog code for thisbelow function using HDL coder?
You can use the real divide hdl optimized block. Other options include the reciprocal block followed by a multiply or the divide...

2年以上前 | 0

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Unable to run HDL QPSK Transmitter and Receive
You need DSP HDL Toolbox to run this example. Please reach out to support to see why you do not have access to this product.

2年以上前 | 0

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AD936x Receiver Transmitter blocks missing in Simulink library
Running the command "which zynqRadioQPSKRxAD9361AD9364SL" should show you where the Simulink model lives in your installation. T...

2年以上前 | 0

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Code Generation for d flipflop
Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you ...

2年以上前 | 0

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Error evaluating 'InitFcn' callback of block_diagram 'hdlcoder_lteofdm_modDetect'. Callback string is 'simParams = hdlcoder_lteofdm_modDetectref_init; simParams = hdlcoder_lteofdm_modDetecthdl_init(simParams);
As John mentioned in the comments, the function mentioned in the Diagnosic Viewer, lteTestModel, is a function in the LTE Toolbo...

2年以上前 | 0

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Enable Not Working on Synchronous Subsystem
The synchronous state control behaves exactly like the HDL would, doing a divide by zero because the reciprocal block is a combi...

2年以上前 | 0

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Test bench can't work for some 'entity' are not compiled in library 'xil_defaultlib'.
System Generator is a third-party blockset provided by Xilinx. For any further questions, please contact Xilinx technical suppor...

2年以上前 | 0

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Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder generates HDL code compliant with Verilog-2001. https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-...

2年以上前 | 1

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How to get fractional delay filter in vhdl using matlab 2021a.
You can look at this example that shows how to quantize the filter before generating HDL.

2年以上前 | 0

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Why is my FFT HDL Optimized block running slower in FIL than Simulink?
This slowdown is due to the time it takes to send the data over from Simulink to the FPGA and back. You can use an Ethernet cab...

3年弱前 | 0

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