OFDM Transmit and Receive Using Xilinx RFSoC Device

This example uses:

This example shows how to simulate and deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm in Simulink® using an SoC Blockset™ implementation targeted on a Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can integrate HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples into the SoC Blockset implementation.

Supported Hardware Platforms

Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit + XM500 Balun card

Design Task

In this example, the design task is to build a wireless communication system with an OFDM transmitter and receiver and implement the system on a Xilinx RFSoC device. This example shows the workflow for designing, simulating, and deploying the OFDM-based transmit and receive algorithm on the hardware. This figure shows the conceptual overview of the example.

The OFDM Transmitter and OFDM Receiver blocks perform high-speed signal processing tasks and make the OFDM-based transmit and receive algorithm well suited for FPGA implementation on the programmable logic (PL) of the radio platform. To implement this algorithm on the PL, the example uses the Simulink® hardware models from the HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples as model references. The example is also equipped with an internal channel to apply carrier frequency offset (CFO) and an HDL additive white Gaussian noise (AWGN) channel from the HDL Implementation of AWGN Generator (Wireless HDL Toolbox) example. Control signals insertCFO and snrdB are provided to tune the channel.

The normalization and denormalization of the CFO involves division and multiplication, which operate at low rate. This characteristic makes the CFO computation well suited for software implementation on the integrated ARM® processing system (PS) of the radio platform.

Design Using SoC Blockset

Create an SoC model soc_OFDM_top as the top model and set the hardware board to Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit. The top model includes FPGA model soc_OFDM_fpga and processor model soc_OFDM_proc, which are instantiated as model references. The top model also includes AXI4-Stream to Software block that share the external memory between the FPGA and the processor.

Create an SoC model soc_OFDM_hwtop as the top model for the simulation of a hardware algorithm with a static configuration. This model includes an FPGA model soc_OFDM_fpga .

RF Data Converter Configuration

An RFSoC device has its RF data converter connected to the PL. To configure the analog to digital converter (ADC) and digital to analog converter (DAC) settings, use the RF Data Converter block. The block provides an interface to the Xilinx RF Data Converter IP in Simulink to model a wireless system destined for implementation on a Xilinx RFSoC device.

To meet the 860 MHz RF carrier frequency and 61.44 MSPS baseband sample rate, configure the RF Data Converter block according to the settings described here and shown in the figure. Set the NCO frequency parameter for the DAC and ADC mixers to 0.860 GHz, and set the DAC and ADC sample rate to 3932.16 MSPS. Choose the values of Interpolation mode (xN), Decimation mode (xN), and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is the desirable value. For this example, the desired value is 61.44 MSPS. This value is calculated and displayed on the block mask as the Stream clock frequency (MHz) parameter after you click Apply. Set the Decimation mode (xN) parameter to 8. The effective sample rate after decimation is 491.52 MSPS. To get the clock cycle (baseband sample rate) to 61.44 MSPS, set the Samples per clock cycle parameter to 8. Similarly, in the DAC tab, set the Interpolation mode (xN) parameter to 8 and the Samples per clock cycle parameter to 8. With these settings, the Stream clock frequency parameter is 3932.16/(8*8) = 61.44 MHz.

Hardware Logic Design

The FPGA model soc_OFDM_fpga contains three subsystems: Vector Interpolation (which is connected to the DAC portion of the RFDC block), Vector Decimator (which is connected to the ADC portion of the RFDC block), and OFDM TxRx.

The Vector Decimator block receives the packed eight samples as 128 bits. The Vector Decimator block decimates input vector samples by 8 and sends them to the OFDM TxRx subsystem. The sample rate after the Vector Decimator block is 61.44 MSPS, as expected by OFDM TxRx for its processing.

The OFDM TxRx subsystem is an enhanced version of the OFDM Transmitter and OFDM Receiver back-to-back modeling from the HDL OFDM MATLAB References (Wireless HDL Toolbox) example. The OFDM TxRx subsystem has two sections: an OFDM Transmit and Receive section and a Status Signal Generation section. OFDM Transmit and Receive includes OFDM Tx Channel OFDM Rx, Prepare Inputs, and Prepare Outputs subsystems.

The OFDM Tx Channel OFDM Rx subsystem includes OFDM Tx, OFDM Rx, Channel Control, and Payload Data subsystems.

The OFDM Tx subsystem is implemented from the HDL OFDM Transmitter (Wireless HDL Toolbox) example.

The OFDM Rx subsystem is implemented from the HDL OFDM Receiver (Wireless HDL Toolbox) example.

The Channel Control subsystem has a White Gaussian Noise Generator subsystem and an Apply CFO subsystem. The White Gaussian Noise Generator has an AWGN generator from the HDL Implementation of AWGN Generator (Wireless HDL Toolbox) example. The Apply CFO subsystem performs the CFO insertion using the NCO (DSP HDL Toolbox) block.

The Select Payload Data subsystem contains an LUT that stores the data bits used for transmitter waveform generation.

In the receive path, the Vector Decimator block receives the packed eight samples with a sample rate of 491.52 MSPS from the RF Data Converter block. The Vector Decimator block decimates input vector samples by 8 and sends them to the OFDM receiver. The sample rate after the Vector Decimator block is 61.44 MSPS, as expected by the OFDM TxRx subsystem for its processing. The OFDM Receiver block sends the processed data to the processor with a sample time of 61.44 MHz. In the transmit path, the OFDM Transmitter block sends the samples to the RF Data Converter block through the Vector Interpolation block. The Vector Interpolation block interpolates the input samples by 8 (491.52 MSPS) and sends them to the RF Data Converter block as a vector of eight samples.

Processor Logic Design

The processor logic contains a read task and a periodic task. The periodic task is a timer-driven task with a periodic time of 1e-2, which is defined in the task manager. The periodic task drives the control and status signals of the hardware algorithm through the AXI4-Lite registers. The model displays status information such as number of frames synchronized, estimated CFO, decoded header information (modType and codeRate), number of header and data CRC pass and failures, number of bits received, and number of bit errors from the OFDM receiver. The controller provides the constellation data and status information to the MATLAB host by using UDP blocks. The RxUDPData and StatusUDPData subsystems relay the constellation and status signals, respective to the host over the UDP protocol.

The read task is an event-based task driven by the arrival of data from the FPGA through DDR memory. This data comprises the constellation data of the selected modulation type. The previous two tasks are modeled under the Processor Algorithm Wrapper subsystem in processor model soc_OFDM_proc and are connected to the Task Manager block at the top level.

Host Model

The processor sends the OFDM Receiver block outputs data and receiver status signals directly back to the host over the Ethernet link by using UDP Write blocks. The IP address of the UDP Write block in the processor model must be configured to the IP address of the host. This interface model, which runs on the host, shows how to receive data from the hardware platform and how to postprocess it.

Simulate

To confirm its basic operation, run the hardware generation model using dataBits stored in the soc_OFDM_databits.mat file. The model callback initialization loads dataBits to the workspace. To access the callback initialization, select MODELING > Model Settings > Model Properties > Callbacks > InitFcn.

Because the model contains a large number of HDL-optimized blocks, and these HDL-optimized blocks require simulation using sample-based signals. It takes a while for the simulation. The figure shows the constellation diagram from the simulation.

To enable the AWGN channel between the OFDM Transmitter and OFDM Receiver, set enableInternalLoopback to true. You can control the channel by using channel impairments insertCFO and snrdB. When you set enableInternalLoopback to false, the OFDM signals are transmitted and received externally through the Tx and Rx antennas, where the channel impairments are added over the air in real time.

If you want to see the complete hardware and software simulation of the OFDM transit and receive algorithm and the controller dynamic configuration, run the soc_OFDM_top model. Run the host model to see the receiver status signals and constellation diagram.

Implement and Run on Hardware

Hardware Setup

Connect the SMA connector on the XM500 Balun card to complete the loopback between the DAC and ADC, according to these connections: DAC229_T1_CH2 (J5) to ADC224_T0_CH0 (J4).

To implement the model on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board option is set to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit on the System on Chip tab of the Simulink toolstrip.

To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.

On the Setup screen, select Build Model and click Next.
On the Select Build Action screen, select Build and load for external mode and then click Next.
On the Select Project Folder screen, specify the project folder and then click Next.
On the Review Memory Map screen, click View/Edit Memory Map to view the memory map and then click Next.
On the Validate Model screen, click Validate to check the compatibility of the model for implementation and then click Next.
On the Build Model screen, click Build to begin building the model. An external shell opens when FPGA synthesis begins. Click Next.
On the Connect Hardware screen, click Test Connection to test the connectivity of the host computer with the SoC board. Click Next to go to the Run Application screen.

FPGA synthesis often takes more than 30 minutes to complete. To save time, you can use the provided pregenerated bitstream by following these steps.

Close the external shell to terminate FPGA synthesis.
Copy the pregenerated bitstream to your project folder by entering this command at the MATLAB command prompt.

copyfile(fullfile(matlabshared.supportpkg.getSupportPackageRoot, ...
 'toolbox','soc','supportpackages','xilinxsoc','xilinxsocexamples', ...
 'bitstreams','soc_OFDM_top-XilinxZynqUltraScale_RFSoCZCU111EvaluationKit.bit'),'./soc_prj');

Click Load and Run to load the pregenerated bitstream and run the model on the SoC board. After the bit file is loaded, open the generated software model.

Run the model in external mode by clicking Monitor & Tune. You can control the configuration from the Simulink model.

Constellation and Status Signals from Hardware

Run the host model to see the received constellation data and receiver status signals. When the host interface model runs successfully, the model displays the constellation diagram and status signals.

Conclusion

This example shows how to integrate the OFDM transmit and receive algorithms on a Xilinx ZCU111 evaluation board using an SoC Blockset implementation and how to verify the design in simulation and on hardware.