Parallel Link Design

Design parallel links such as DDR

The Parallel Link Designer app provides a dedicated system-level design and analysis environment for parallel links. Capture your parallel link designs graphically and experiment with different physical layouts and parameter sweeping to determine setup/hold timing and voltage margins for high-speed parallel links. Analyze parallel interfaces for compliance with timing and signal integrity constraints.

Use the Parallel Link Designer app to configure parallel links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE and to conduct waveform and timing data analysis to analyze your custom parallel links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your parallel link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.

Apps

Parallel Link Designer	Analyze PCB designs for parallel link applications
Signal Integrity Viewer	View the signal integrity results of Serial Link Designer or Parallel Link Designer app

Objects

`SignalIntegrityProject`	Create Signal Integrity Toolbox project object
`SignalIntegrityInterface`	Return interface object of given Signal Integrity Toolbox project object
`SignalIntegritySheet`	Return sheet object of given Signal Integrity Toolbox interface object
`SignalIntegrityState`	Return state object of given Signal Integrity Toolbox sheet object
`SignalIntegritySimulation`	Return simulation object of given Signal Integrity Toolbox sheet object
`SignalIntegrityWaveform`	Return waveform object of given Signal Integrity Toolbox simulation object

Topics

Parallel Link Design Basics

Clock Modes
Learn about different clock modes in AMI models.
PAMn Capabilities
Design and simulate systems and test AMI models using PAMn signaling.
Elements in Link Designer Apps
List of elements used by the Serial Link Designer and Parallel Link Designer apps.
Available Operations in Signal Integrity Viewer
Refresh, zoom, use markers and thresholds, and modify display in Signal Integrity Viewer app.
Solution Space
Solution space variables, permutation mode and case mode.
Loss in Transmission Line Corners
Learn how loss behaves in various transmission line corners.
Access Project Data from MATLAB Command Window
Access read-only project data from MATLAB^® command window to create your own evaluation environment.
Run Parallel Simulations in Signal Integrity Toolbox
Reduce the time required to run a complete set of simulations by running the simulations in parallel with Parallel Computing Toolbox™.

Configure Parallel Link Projects

Simulation Parameters Used in Parallel Link Design
Set parameters to control SPICE simulation and statistical, time domain, and waveform analysis.
Specify Corner Conditions in Parallel Link Design
Specify process corners and etch corners to simulate in parallel link project.
Stimulus Patterns in Parallel Link Design
Define stimulus patterns for time domain analysis in parallel link project.
STAT Mode
Learn how STAT mode works in the Parallel Link Designer app.
S-Parameters in Parallel Link Projects
Learn how to import S-Parameters and use it in analysis.
Model Lossy Transmission Lines in Parallel Link Designer
Learn the mathematics behind the lossy multi-conductor transmission line models.
Model Jitter and Noise While Designing Parallel Link
Add TX clock jitter, RX clock jitter, RX clock recovery jitter, and noise.

Pre-Layout Analysis

Pre-Layout Analysis of Parallel Link
Learn the basics of pre-layout analysis.
Customize Parallel Link Project for Pre-Layout Analysis
Edit transmission line models, designators, S-parameters, and IBIS files to customize pre-layout analysis.
Results of Pre-Layout Analysis in Parallel Link
View, interpret, and debug the pre-layout analysis results.

Post-Layout Verification (Requires RF PCB Toolbox)

Post-Layout Verification of Parallel Link
Verify system-level SI and timing margins of PCB design databases.
Stackup and Extraction Control in Parallel Link Project
Edit stackups and control padstack models.
Via and Stackup Management in Parallel Link Project
Manage vias and stackups using Stackup Editor and PadStack Editor.
Post-Layout to Pre-Layout Extraction
Create topologies from extracted PCB data.

Results to View with Signal Integrity Viewer

Network Characterization Results
Table of data and waveforms to view in the Network tab after performing network characterization.
Statistical Analysis Results
Table of data and waveforms to view in the Statistical tab after performing statistical analysis.
Time Domain Analysis Results
Table of data and waveforms to view in the time domain tab after performing time domain analysis.
Interpreting Waveform, Eye Diagram, and Timing Results
Waveform, eye diagram, and timing results interpretations in Parallel Link Designer.
Eye Measurement and Reporting
Measure and report eye diagram metrics.
Waveform Analysis
Analyze waveform overshoot and other quality metrics.
Waveform Analysis Parameters and Thresholds
Learn about the parameters and thresholds used in waveform analysis using the Parallel Link Designer app.
Waveform Reports
Results of waveform and timing analysis.
Widebus Crosstalk Analysis
Pre-layout crosstalk analysis in the Parallel Link Designer app.
Managing Simulation Data and Results
Quickly and efficiently sort through the simulation data and results of the link design project.
Advanced Visualization Using Signal Integrity Viewer
Plot frequency and time domain waveforms and results against single or multiple variables.

Featured Examples

Post-layout of DDRx Interface with CPU and DIMMs

Demonstrates the use of Parallel Link Designer in the Signal Integrity Toolbox™ in MATLAB® to set up a post-layout analysis of a DDRx interface on a Main Board having a CPU connected to two DIMM slots to verify that waveform quality and timing margins are met by the PCB database. Many of the steps illustrated in this example are also applicable to Serial Link Designer for post-layout analysis of SERDES links.

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DDR5 IBIS-AMI with Clock Forwarding

Use Signal Integrity Toolbox™ for MATLAB to analyze a DDR5 interface with the IBIS-AMI feature Clock-Forwarding enabled for analysis of system margins. IBIS BIRD 204, "DQ_DQS GetWave Flow for Clock Forwarding Modeling," adds the ability to pass in an external Clock signal (or Strobe, as appropriate) to an Address (or Data) IBIS-AMI receiver GetWave model using the clock_times pointer defined by the IBIS specification. A new AMI Reserver Parameter, Rx_Use_Clock_Input, is used to enable this functionality.

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DDRx Timing and Waveform Mask Analysis

Use the Parallel Link Designer app to perform timing analysis for the DDR (Double Data Rate) family of memory interface protocols. You can use either Setup and Hold margins or by waveform eye-diagram compliance masks to perform the timing analysis. The DDR Memory Down (DDR4_MD) example kit uses both timing and waveform mask analysis. Specifically for DDR4 systems, timing analysis is performed on clock-address/command interface, and waveform compliance masks are applied to strobe-data(DQS-DQ) interface. Other DDR types may use only timing analysis, or only waveform mask analysis or a blend depending on individual standards.

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Data Mining With Signal Integrity Viewer

For those experienced using Serial Link Designer, you are probably aware that even the simplest simulations can produce mountains of data and sorting through the data can be time consuming. As the complexity of the channel and number of variables increase, sorting through that data can be ever more daunting. This example is set up to show some of the tools available to give the user control, to focus in on the results and variables of interest and make design decisions on large data sets.

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Low-Power DDR5 Architectural Kit

Implement a low-power DDR5 (LPDDR5) interface for pre-layout analysis or post-layout verification.

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DDR5 Implementation Kit

Implement a 1-slot generic DDR5 RDIMM interface for pre-layout analysis or post-layout verification.

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