Soft Charge Control

R2026b

Generate thyristor gate pulses for soft-charging a DC bus capacitor

Since R2026b

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Libraries:
Power Converter Control with Motor Control Blockset / Control / Power Factor Correction

Description

The Soft Charge Control block generates gate pulses to control the thyristor during DC bus capacitor soft-charging in a PFC stage. Soft-charging limits the inrush current into the DC bus capacitor at startup by progressively delaying the thyristor turn-on angle until the capacitor is fully charged.

The block accepts the grid phase angle in the range [0, 2π] at the θGrid input and an incremental angle (Δθ) at the Δθ input. The incremental angle controls the rate at which the thyristor turn-on time is ramped during the charging sequence. Use the formula Δθ = (π/2 / T_charge) × T_s, where T_charge is the time required to charge the DC bus capacitor in seconds and T_s is the block sample time in seconds.

Assert the En enable input to start the soft-charge sequence. The block outputs high-side gate pulses (GH), low-side gate pulses (GL), a completion status flag (Status), and diagnostic information (Info).

Ports

Input

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Instantaneous grid phase angle in radians, in the range [0, 2π], specified as a scalar. Obtain this value from a PLL block that tracks the AC grid phase. The block uses this angle to determine the thyristor turn-on timing relative to the grid voltage zero-crossing.

Data Types: double | single

Angle increment in radians that controls the rate at which the thyristor turn-on delay decreases during the soft-charge sequence, specified as a positive scalar. Compute this value as Δθ = (π/2 / T_charge) × T_s, where T_charge is the desired capacitor charging time and T_s is the block sample time. A smaller value extends the charging duration and reduces peak inrush current.

Data Types: double | single

Enable signal that activates the soft-charge sequence when asserted (nonzero), specified as a scalar. Assert this signal when the system is ready to begin charging the DC bus capacitor. The block begins generating gate pulses when this input is nonzero.

Data Types: double | single

Output

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Gate pulse for the high-side thyristor, output as a scalar Boolean. Connect this signal to the gate input of the high-side thyristor in the soft-charge circuit.

Data Types: double | single

Gate pulse for the low-side thyristor, output as a scalar Boolean. Connect this signal to the gate input of the low-side thyristor in the soft-charge circuit.

Data Types: double | single

Status flag that is asserted (nonzero) when the soft-charge sequence completes, output as a scalar. Use this signal to detect when the DC bus capacitor is fully charged and the bypass contactor can be closed.

Data Types: double | single

Diagnostic information bus for the soft-charge sequence, specified as a bus. The bus contains a single field:

FiringAngleRef — the current thyristor firing angle reference in radians, in the range [0, π/2]. The block uses this value to track the delay angle that is ramped from π/2 (maximum delay, minimum current) down toward 0 as charging progresses. Monitor this field to observe the progression of the soft-charge sequence and to verify the ramp rate set by the Δθ input.

Data Types: bus

Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2026b