ADC Design

Simulation speed is key to bringing analog-to-digital convertors (ADCs) to market quickly. Because Simulink® employs an abstract behavioral modeling approach, you can use it to create an ADC design in a fraction of the time required by SPICE tools. Simulink dramatically reduces simulation time from days to hours or minutes, giving designers the time to optimize their systems and thoroughly test their designs. Doing rapid ADC design with Simulink enables faster parameter sweeps, allowing engineers to perform detailed verification in less time.

Many companies, including Epson Toyocom, Infineon, Alcatel-Lucent, and others, have adopted Simulink for ADC design for just these reasons. Epson Toyocom reports a substantial cut in simulation time: "Circuit-level simulations took three days. Using MATLAB and Simulink, we reduced simulation time to just one minute," said Jun Uehara at Epson Toyocom.

The Simulink video below shows how quickly you can simulate a second-order sigma-delta ADC.

Rapidly simulate a second-order sigma-delta modulator, modeling analog and digital components in the same model at the same time.

Digital Predistortion

Digital predistortion is simple in theory, but difficult in practice. Engineers need to control sophisticated test equipment, analyze complex data, and build algorithms for DSPs or FPGAs. These individual tasks can require different tools, adding to the complexity. MATLAB® provides a unifying environment for all these tasks. Engineers can use MATLAB to control power amplifier measurements, create digital predistortion algorithms, and generate C and HDL code for implementation.

Nujira built their digital predistortion and envelope tracking measurement system using MATLAB. In addition, MATLAB controls their Tektronix, Rohde & Schwarz, and Agilent test equipment via the SCPI and GPIB interfaces and automates their testing process. Commscope uses MATLAB to analyze their large power amplifier data sets to create their digital predistortion algorithms. Alcatel-Lucent employed a similar process to develop their algorithms, and used Xilinx® System Generator to develop digital predistortion code for their Xilinx FPGAs: "The quality of the generated code was so high that we didn't make a single change in the production system," said Dr. Rudolf Wessel, engineering manager at Alcatel-Lucent.

Create a digital pre-distortion model with MATLAB , including fitting model parameters to measured data in a single line of code and testing the results.

PLL Design

SPICE models are accurate, but extremely slow when it comes to phase-locked loop (PLL) design. The feedback loop is a difficult challenge for the underlying SPICE simulation engine. By contrast, Simulink® takes a different simulation approach that results in very fast PLL design. With its control design heritage, Simulink has a simulation engine that is extremely efficient at simulating systems with feedback loops. The combination of behavioral modeling and a faster approach to simulation enables engineers to cut simulation times for PLL designs from days to hours or minutes.

Because of these much shorter PLL design times, many companies have adopted Simulink for PLL design. Liu Xin, staff design engineer at IDT-Newave reports: "In just one month, our system-level engineers and circuit designers determined optimal jitter performance with PLLs."

These time-saving benefits also extend to more recent all-digital PLL designs, as Russell Mohn of Epoch Microelectronics explains: "Simulink behavioral simulation is much faster than circuit-level simulation, and as a result, we can complete many simulations in one day, experimenting with different implementation ideas for the functional blocks."

Use Mixed-Signal Blockset to model a commercial off-the-shelf integer-N PLL with dual modulus prescaler operating around 4GHz. Verify the PLL performance, including phase noise, lock time, and operating frequency.


SERDES simulation can cause problems for circuit simulators. Circuit complexity coupled with high data rates can slow simulations to a crawl, which threatens project delivery times and limits the scope for design exploration.

SERDES design using Simulink® is much faster. Simulink's sophisticated time handling, coupled with its controls design background, mean that circuit loops can be simulated quickly. Impairments such as noise and jitter can be included in the system-level simulation, increasing accuracy. As William Walker of Fujitsu states: "By including circuit-level simulation results in our Simulink models, we can simulate millions of cycles with the accuracy needed to account for noise and other transient effects. Simulink is the only tool fast enough for our jitter-tolerance simulations."

Though cosimulation and links to other EDA tools, system-level SERDES designs can be linked to EDA tools for the next stage of the design process.