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Marc Erickson

Last seen: 14日 前 |  2020 年からアクティブ

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  • 3 Month Streak
  • Knowledgeable Level 2
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Error running simulink with QuestaSim. Failed to connect to server. Make sure loaded HDL simulator library is using shared memory.
HDL Verifier cannot support the Intel FPGA Edition of ModelSim since that version of the simulator does not support PLI applicat...

5ヶ月 前 | 1

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I am unable to compile and execute SystemC code generated from a Simulink model
You appear to have a missing the specification of the systemc library and so it is showing up as an empty string in the linker l...

5ヶ月 前 | 0

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Error: Failed to load shared library "xsim.dir/design/xsimk.so"
For linux, there are two key requirements: You must use the supported version of Vivado for the version of MATLAB you are usin...

6ヶ月 前 | 0

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How to call vivado from matlab for cosimulation
The Vivado Simulator cosimulation process is different than that for ModelSim. For Vivado, a shared library containing the Vivad...

7ヶ月 前 | 0

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Can ModelSim Altera Starter Edition be used for HDL cosimulation?
(Moving Eric's response to be an Answer.) No, HDL Verifier generally requires one of the versions of ModelSim or Questa that is...

8ヶ月 前 | 0

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How to include Vivado in cosimulation wizard hdl simulator ?
There is nothing that needs to be done to include "Vivado Simulator" in the drop-down selection of the Cosimulation Wizard. The ...

8ヶ月 前 | 0

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Error using () Data type mismatch at signal 'c_out'.This port expects a Logic data type of size 1
The module port declarations are (implicitly) declaring c_out and sum as net types of wire and data type of logic (1 bit and 4 b...

1年以上 前 | 0

回答済み
xcelium with HDL Verifier
The nclaunch MATLAB function is a MATLAB front-end to creating a shell script for compiling and launching Xcelium. Its name is h...

1年以上 前 | 0

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Which xcelium version is supported with HDL Verifier?
Hi Fatimah, As you have found, the documentation states supported third party tool versions at Supported EDA Tools and Hardware...

1年以上 前 | 0

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How to update HDL verifier block when VHDL source changes its port definition?
You have cited two ways to update the interface: Re-running the cosimulation wizard or using the block mask "Ports" tab and usin...

1年以上 前 | 0

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Import HDL Code for HDL Cosimulation Block with VHDL-2008
I could not find any way to directly specify the option for the project-based compilation. Instead, one must use the optoins set...

2年弱 前 | 0

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Error in FIL simulation at the second time it's running
Double check that the bitstream you are using was created with the same version of Simulink as you are running your model with. ...

2年以上 前 | 0

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how to solve coder.internal.Float2FixedConverter.runTestBenchToLogDataNew ?
The cited package, Float2FixedConverter, is available through the Fixed Point Designer or HDL Coder products. To use the System...

2年以上 前 | 0

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Is it possible to generate DPI model of PLL Testbench block and use it inside SystemVerilog/UVM testbench?
A very interesting idea! The SystemVerilog DPI component generation currently supports only Fixed Step solvers to allow easy in...

3年弱 前 | 0

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TLM Generator HDL coder
The SystemC environment variables are not set for the include path. In the demo, the section, "Select TLM Compilation View", go...

約4年 前 | 0

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