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Michael Felger


Last seen: 2日 前 |  2019 年からアクティブ

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質問


How to set Unconditional Transition State for Else Statement in HDL Coder with a Counter?
Hi, in the HDL Coder Guideline, it is recommended to insert an unconditional Else transition: "Insert Unconditional Transition ...

23日 前 | 1 件の回答 | 0

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質問


Simulink - Bus Creatro - how to set unused bus to "zero"?
Hi, in my model, I use many buses with many more signals, which go to different subsystems. For different testcases, only some...

8ヶ月 前 | 1 件の回答 | 0

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How do you generate a registered output from Stateflow?
Update: starting with R2022b, the ClockDrivenOutput parameter for stateflow is available for Moore charts. https://de.mathworks...

11ヶ月 前 | 0

質問


The top design unit selected for HDL code generation may not be inside a triggered subsystem.
Hi, why was this limitation intoduced in Matlab? In Matlab 2019, this limitation is not there. I wanted to port my model to Ma...

2年弱 前 | 1 件の回答 | 0

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質問


HDL Coder reset - asynchronous and synchronous possible?
Hi, is it possible to generate HDL code with both, asynchronous and synchronous reset? https://de.mathworks.com/help/hdlfilter...

約4年 前 | 1 件の回答 | 0

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質問


stateflow hdl code generation hierachy flatten
Hi, I use stateflow for HDL-Code generation of an fsm. The stateflow has several hierachies. The hierachies are mainly for rea...

約4年 前 | 1 件の回答 | 0

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質問


HDL Coder custom file header - settings
Hi, generating VHDL-Code with HDL coder, there are some informations (like filename, date, module) in the default header. It ...

4年以上 前 | 1 件の回答 | 0

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質問


HDL Coder to / downto order
Hi, I'm using HDL Coder to generade VHDL code for a simulink block. In the entity, the port order is generated as follow: for...

4年以上 前 | 2 件の回答 | 0

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How do you generate a registered output from Stateflow?
I have exactly the same question!

4年以上 前 | 0

質問


HDL Coder 'abs' : Double and complex data types not supported.
I'm using a simulink model to generate HDL code for simulation, with double values. The error is clear, as "Double and complex ...

4年以上 前 | 1 件の回答 | 0

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質問


stateflow variant states possible?
Is is possible to add variants of a state inside a stateflow diagram, similar to variant subsystems in simulink?

5年弱 前 | 3 件の回答 | 1

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質問


Why don't i get a data type mismatch error?
Hi, following is inside my simulink model: a Stateflow chart, inside this chart: a 2-dimensional array a(5,5), data type...

5年弱 前 | 0 件の回答 | 0

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質問


HDL Coder disable Clock Enable output port
How can I disable the Clock Enable output port in generated VDHL-Code? I can specify the name In HDL Code Generation -> Global ...

約5年 前 | 2 件の回答 | 0

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質問


How do I display logged local data of stateflow in Logic Analyzer
I would like to log a Local variable in a stateflow diagram and view it in the Logic Analyzer together with other signals. I've...

約5年 前 | 1 件の回答 | 0

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