HDL Verifier Support Package for Xilinx FPGA Boards
Debug and test HDL code on Xilinx FPGAs and Zynq SoCs.
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更新
2024/4/3
HDL Verifier™ Support Package for Xilinx® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Xilinx FPGA and Zynq® SoC boards. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code.
The FPGA Data Capture capability lets you observe signals from your design in MATLAB while the design is running on the Xilinx FPGA or Zynq SoC. Then use these signals in MATLAB or Simulink for analysis and verification, or view them using the Logic Analyzer in DSP System Toolbox.
AXI Manager IP included in the support package enables you to read from or write to on-board memory locations directly from MATLAB.
MATLAB リリースの互換性
作成:
R2014a
R2014a 以降 R2024a 以前と互換性あり
プラットフォームの互換性
Windows macOS (Apple シリコン) macOS (Intel) Linuxカテゴリ
- Code Generation >
- Code Generation > HDL Verifier >
- FPGA, ASIC, and SoC Development > HDL Verifier >
- Code Generation > HDL Coder > HDL Coder Supported Hardware >
- FPGA, ASIC, and SoC Development > HDL Coder > HDL Coder Supported Hardware >
- FPGA, ASIC, and SoC Development >
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