HDL Coder output port type needs to be std_logic_vector (8 downto 0)

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Rick Policy
Rick Policy 2021 年 6 月 28 日
回答済み: Kiran Kintali 2021 年 6 月 30 日
I am currently evaluating Simulink's HDL coder for VHDL and need some help after searching the internet for hours...
My simple design is an adder that adds two uint8 numbers. It seems like uint8 inputs/output ports maps nicely to std_logic_vector(7 downto 0). However, how would one generate a std_logic_vector(8 downto 0) output port. The built in datatypes for input/output ports don't seem to match anything other than 8/16 bit integers.
Any help would be appreciated...

回答 (1 件)

Kiran Kintali
Kiran Kintali 2021 年 6 月 30 日
Consider using hdlsetup command, it puts the model in ASIC/FPGA mode which generates full-precision arithmetic suitable for ASIC/FPGA settings.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Subsystem IS
PORT( In1 : IN std_logic_vector(7 DOWNTO 0); -- uint8
In2 : IN std_logic_vector(7 DOWNTO 0); -- uint8
Out1 : OUT std_logic_vector(8 DOWNTO 0) -- ufix9
);
END Subsystem;
ARCHITECTURE rtl OF Subsystem IS
-- Signals
SIGNAL In1_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL In2_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Add_out1 : unsigned(8 DOWNTO 0); -- ufix9
BEGIN
In1_unsigned <= unsigned(In1);
In2_unsigned <= unsigned(In2);
Add_out1 <= resize(In1_unsigned, 9) + resize(In2_unsigned, 9);
Out1 <= std_logic_vector(Add_out1);
END rtl;

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