Why can I not change the architecture of my subsystem to Black Box?
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I am using R2018b. My end goal is to use FPGA in the Loop programming. I have verilog files that I want to include as a black box but I cannot change the architecture of my simulink subsystem to a blackbox.
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Raghav Singhal
2019 年 2 月 20 日
Please see this documentation page for details on generating a black box interface:
Antti Mattila
2019 年 12 月 30 日
I seem to have the same problem. The "BlackBox" architecture option is not available for a subsystem. (I'm using 2018b also).
For some subsystem/refrenced models it is. This seems arbitrary.
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Sina Aghli
2020 年 1 月 18 日
I'm having the same issue(R2019a), has this feature been deprecated?
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Sina Aghli
2020 年 1 月 18 日
I create a HDL/Subsystem and then rightckick then HDL Code -> HDL Block Properties ...
then in "HDL properties::Subsystem" window under Implementation->Architecture, the only available option is "Module" and there is no blackbox option
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