Using unit delay with HDL Code Generator

1 回表示 (過去 30 日間)
Maria
Maria 2018 年 10 月 25 日
Hello! I'm trying generate HDL code for next block, which calculates derivative of input signal with Sample Time = 200 us.
How I can provide it for FPGA with clock 100 MHz (clock period 10 ns)? I must delay signal in "Delay" block for one sample time = 200 us, but I have delay for one period of clock = 10 ns.

回答 (0 件)

カテゴリ

Help Center および File ExchangeHDL Coder についてさらに検索

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by