How do vectorized ports in hdl coder work?

Hi,

i'm working with a speedgoat real-time target machine with an IO323 FPGA Card and HDL Coder. On this site: https://de.mathworks.com/help/xpc/ug/fpga-subsystem-plan.html i read that i can use vectorized ports to synchronize the PCIe Access of several Registers. I tried to achieve that with a simple example. Inside the FPGA Subsystem i muxed two constants and connected the vector Signal to an Output port.

Then i use the HDL Workflow advisor to map that outport to be a PCI Interface.

In my Realtime Model i tried to display the two values on a target scope.

My problem is that both entries of the vector show the value of the second constant (value = 2).

As the HDL Coder proposes, I selected the Scalarize vector ports option.

Is there any special setting i have to do?

I use Matlab R2016a (Version 9.0) with HDL Coder Version 3.8

Answer 1

[Wang Chen]

Hi Jay,

The expected behaivor is to get [1 2] value for the vector port.

This should already be fixed in newer version of the HDL Coder.

Could you contact MathWorks customer support if you still see this issue?

Thanks,

Wang