error after targheting xilinx Virtex UltraScale+ VCU118.

hi, I targheting a xilinx virtex ultrascale+ vcu118 board following the procedure provided by the matworks guides ( https://it.mathworks.com/help/hdlcoder/ug/register-a-custom-reference-design.html , https://it.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-xilinx-zynq-platform.html ). later I added the reference design on the matlabroot ([matlabroot '/toolbox/hdlcoder/hdlcoderdemos/customboards']) and i ran command : 1)addpath(fullfile(matlabroot,'toolbox','hdlcoder','hdlcoderdemos','customboards','VCU118'));

2)hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2021.1\bin\vivado.bat');

when i try to use HDL coder on simulink (HDL code => HDL workflow advisor => set target => target workflow = " ip core generation" => target platform = " vcu118") at this point the hdl coder generate an error.

****the FPGA device "Virtex UltraScale+/xcvu9p/flga2104/-2" used in " Virtex Ultrascale+....." is not supported by your current synthesis tool, "Xilinx Vivado 2021.1" .... ****

But synthesis tool used supported this device, is present in board catalog.

attached there are custom reference design and immage of error.

thank for help.

Answer 1

[Kiran Kintali]

Possible pilot error in setting up the custom reference design or board support package.

Please contact https://www.mathworks.com/support.html for additional help.

www.mathworks.com/help///hdlcoder/ug/register-a-custom-reference-design.html

Register a Custom Reference Design - MATLAB & Simulink