NR HDL SIB1 Recovery for FR2
This example shows how to design a 5G NR system information block 1 (SIB1) recovery model that is optimized for HDL code generation and hardware implementation and that supports frequency range 1 (FR1) and frequency range 2 (FR2).
5G cell towers can operate in either FR1 or FR2 frequency bands. FR1 covers frequencies up to 6 GHz, and FR2 covers frequencies above 6 GHz, including the millimeter wave band. SIB1 recovery requires cell search, master information block (MIB) decoding, recovery of the SIB1 grid (the area of the resource grid containing CORESET0 and SIB1), and decoding of the CORESET0 PDCCH and SIB1 PDSCH from the SIB1 grid. The process of FR1 Cell Search and MIB recovery are described in the NR HDL Cell Search and NR HDL MIB Recovery examples respectively. The additonal models used to implement FR1 SIB1 grid recovery, CORESET0 decoding, and SIB1 decoding are described in the Hardware Accelerators for NR SIB1 Recovery example. This example introduces functionality that is required to support FR2 and the process of upgrading an existing FR1 design.
The Simulink® models described in this example are fixed-point HDL-optimized implementations of SIB1 recovery for 5G NR FR1 and FR2. This example is one of a related set, for more information see NR HDL Reference Applications Overview.
This example uses these files.
nrhdlSIB1Recovery.slx: This Simulink model combines the processing of the SSB detector, SSB decoder, SIB1 demodulator, CORESET0 decoder, and SIB1 decoder into an integrated model illustrating the complete SIB1 grid recovery process. This model references the
nrhdlDDCCore.slx: This model implements a DDC to create sample streams for SIB1 and SSBs.
nrhdlSSBDetectionCore.slx: This model implements the SSB detection algorithm.
nrhdlSSBDecodingCore.slx: This model implements the SSB decoding algorithm.
nrhdlPolarDecodingChainCore.slx: This model implements the common polar decoding chain.
nrhdlSIB1DemodulationCore.slx: This model implements the SIB1 Demodulation algorithm.
nrhdlCORESET0DecodingCore.slx: This model implements the CORESET0 decoding algorithm.
nrhdlLDPCDecodingChainCore.slx: This model implements the SIB1 LDPC decoding algorithm.
Simulink Data Dictionary
nrhdlReceiverData.sldd: This Simulink data dictionary contains bus objects that define the buses contained in the example models.
runSIB1RecoveryModelFR2.m: This script uses the MATLAB reference to perform the search mode of the SSB detection algorithm, then runs the
nrhdlSIB1RecoverySimulink model to demodulate and decode the SSB, and then demodulate the SIB1 grid. The script performs CORESET0 and SIB1 decoding using either MATLAB code designed for embedded software or the hardware accelerators in the
nrhdlexamples: This package contains the MATLAB reference code and utility functions for verifying the implementation models.
This section describes the changes to the SSB detection MATLAB reference and Simulink implementation in the NR HDL Cell Search example that are required to support FR2.
The SSB detection algorithm performs search and demodulation with a given subcarrier spacing (SCS). The SCS options are 15 kHz or 30 kHz for FR1 and 120 kHz or 240 kHz for FR2. To add FR2 functionality, the new SCS options must be supported. The detector searches for SSBs by downsampling the received signal to one of the rates shown in the table according to the SCS. The signal is then cross-correlated with the PSS sequences.
SCS (kHz) Sample Rate (MHz) _________ _________________ 15 3.84 30 7.68 120 30.72 240 61.44
To accommodate the increased bandwidth requirement of the SSBs in FR2, an input sampling rate of 61.44 Msps is used for the
nrhdlSSBDetectionCore model (compared to 7.68 Msps for the FR1 design). The timing reference units are unchanged and still measured in samples at 61.44 Msps. The timing reference counters increment in steps of 16, 8, 2, and 1 for SCS of 15, 30, 120, and 240 kHz, respectively. The
SCS selection subsystem inside
nrhdlSSBDetection performs the first processing step for SSB detection. This subsystem creates the data streams for each SCS option by successively downsampling the data with halfband filters. All four streams are aligned, enabling the timing reference to be maintained when switching between different subcarrier spacings. The signal processing chain implemented in the
nrhdlSSBDetectionCore is shown. A single SCS data stream is selected for downstream processing.
The selected SCS data stream is correlated against each of the three PSS sequences to detect SSBs. The FPGA implementation of these correlators in the time domain uses 144 DSPs. A frequency domain overlap-add method is used to minimize the DSP usage at the expense of a small increase in latency. This figure shows the overlap-add correlation in the
nrhdlSSBDetectionCore model. The subsystem computes the four stages of the overlap-add method: FFT, multiplication by the three sets of frequency domain coefficients (one for each PSS), IFFT, and overlap and add of subsequent windows. This implementation uses one FFT, three complex multipliers, and three IFFTs, requiring 48 DSP blocks in total.
This section describes the changes to the SSB decoding MATLAB reference and Simulink implementation in the NR HDL MIB Recovery example that are required to support FR2.
The SSB decoding algorithm decodes the broadcast channel (BCH) contained in the SSB. The decoding process outputs the MIB and the beam index of the detected SSB. In FR1, the maximum number of SSBs that can be independently beamformed is 8. FR2 supports transmitting up to 64 SSBs, each on their own beam. The contents of the MIB between FR1 and FR2 differs to accommodate the increase in the maximum number of beams.
nrhdlexamples.ssbDecode function and
nrhdlSSBDecodingCore model accept
Lmax as an input.
Lmax is the maximum number of beams that can be transmitted by a cell tower, and its value depends on the carrier frequency. Valid settings for
Lmax are 4 or 8 for FR1 and 64 for FR2.
Lmax affects the descrambling in the BCH processing subsystem and how the final BCH payload is parsed.
SIB1 Grid Demodulation
This section describes the changes to the SIB1 demodulation MATLAB reference and Simulink implementation in the Hardware Accelerators for NR SIB1 Recovery example that are required to support FR2.
The SIB1 demodulation algorithm performs OFDM demodulation of the SIB1 grid, and includes the lookup tables required to identify the time and frequency resources which contain the SIB1. The SIB1 grid is modulated with a SCS set by the scsCommon field in the MIB. The SCS options are 15 kHz or 30 kHz for FR1 and 60 kHZ or 120 kHz for FR2. To incorporate the wider FR2 bandwidth the FR2 algorithm requires an input sample rate of 122.88 Msps. This is the minimum sampling rate which results in a power of 2 FFT size for FR2 configurations.
For SCS 15 and 60 kHz a 2048-point FFT is used, for 30 and 120 kHz a 1024-point FFT is used. To compute the FFT for the FR1 SCS options, the input sample stream must be downsampled from the input rate of 122.88 Msps to 30.72 Msps. The FR2 SCS options use the input data unmodified. The
Frequency Range Selection subsystem creates the two data streams and corresponding timing references for each frequency range. The
FR1 Downsample subsystem uses two cascaded halfband filters to create the FR1 data and the input data is used directly for FR2. The output from the subsystem is selected based on
Lmax, a value of 2 indicates FR2 otherwise FR1 is selected.
SIB1 Config subsystem is updated to include the additional lookup tables required to generate the
coreset0TimingOccasion signals for the FR2 use case.
This section describes the changes to the DDC MATLAB reference and Simulink implementation in the NR HDL Cell Search example that are required to support FR2.
To accomodate the increased bandwidths of the SSBs and SIB1 in FR2, an input sampling rate of 491.52 Msps is used (compared to 61.44 Msps for the FR1 design). This input rate gives the receiver sufficient bandwidth to sample the SSB and SIB1 subcarriers, provided that the signal is centered on the SSBs. It also includes overhead for the coarse frequency search. This bandwidth allows for MIB and SIB1 recovery without retuning the center frequency of the frontend. To meet the throughput requirements and avoid errors during timing closure, the design uses a clock rate of 245.76 MHz with two samples per clock.
The SIB1 stage creates the SIB1 outputs using two cascaded halfband filters. The first filter operates on the input data stream and downsamples to create an intermediate stream at 245.76 Msps. This downsample reduces the frame size from two samples per clock to one. All downstream processing is performed on scalar data, with the valid duty cycle reducing through each filtering stage. The SSB stage creates the SSB outputs by using a single halfband to implement the filter and downsample from the 122.88 Msps SIB1 rate to the 61.44 Msps rate required for SSB detection.
SIB1 Recovery Simulation Setup
The block diagram shows the simulation setup implemented by this example. The orange blocks highlight the comparison points between the MATLAB reference and the Simulink HDL implementation. The
runSIB1RecoveryModelFR2 script runs the simulation, the MATLAB code represents the software control algorithm and the Simulink simulations perform the FPGA processing. 5G Toolbox™ functions are used to generate a test waveform. MATLAB reference code is used to perform the SSB search stage in place of running the Simulink simulation. The MATLAB reference provides equivalent results and improves simulation speed because it runs faster than the Simulink simulation. The results of the MATLAB SSB search is passed to both MATLAB and Simulink implementations of SIB1 recovery, and the output grids are directly compared. The Simulink SIB1 grid is decoded by one of two methods. The default option uses the
nrhdlSIB1Recovery model to simulate the hardware accelerators for CORESET0 and SIB1 decoding. The second option uses a MATLAB-only decode algorithm. When the design is deployed to an SoC the first option reduces the computations performed by the embedded processor by offloading the calculations to the FPGA. The second option performs all processing in software allowing for the algorithm to be easily modified and updated without rebuilding the FPGA bitstream.
SIB1 Recovery Simulation
runSIB1RecoveryModelFR2 script to run a SIB1 recovery simulation. The script displays its progress at the MATLAB command prompt, and produces plots of inputs and outputs for analysis. The script also supports multiple simulation cases. The full set of cases, and their parameters, are shown.
Simulation Case SSB Pattern Subcarrier Spacing Common PDCCH Config SIB1 SNR dB Strongest SSB index Lmax _______________ ___________ _________________________ _________________ ______ ___________________ ____ "SimCase 1" "Case D" 120 41 10 2 64 "SimCase 2" "Case E" 120 20 2 0 64 "SimCase 3" "Case A" 15 116 5 4 8 "SimCase 4" "Case C" 30 4 20 0 8
This example shows the results of running "SimCase 1". The resource grids produced by MATLAB and Simulink are displayed along with their relative mean squared error (MSE). This comparison verifies that the Simulink implementation closely matches the MATLAB reference. The grid plots are labelled to highlight the decoded PDCCH and PDSCH. The final stage of the script decodes CORESET0, displays the DCIs, and decodes SIB1. The result of the SIB1 decode is displayed, and the SIB1 bits from MATLAB and Simulink are compared to verify that they match.
Generating test waveform. Searching for SSBs using MATLAB reference. NCellID2 timingOffset pssCorrelation pssEnergy frequencyOffset ________ ____________ ______________ _________ _______________ 0 8800 2.0719 2.3012 5504 0 10992 0.40044 0.59184 2703 0 17568 0.24485 0.44337 5901 0 19760 0.73269 0.93887 6647 0 24144 0.52003 0.7229 3062 0 26336 0.4873 0.72059 5132 0 32944 0.90865 1.1301 5085 0 35136 0.5211 0.72334 5414 Recover the SIB1 grid using MATLAB reference. Decoding the SSB using the MATLAB reference. Recovering the SIB1 grid using the MATLAB reference. Recover the SIB1 grid using Simulink model. Running nrhdlSIB1Recovery.slx ### Starting serial model reference simulation build. ### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date. ### Model reference simulation target for nrhdlDDCCore is up to date. ### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date. ### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date. ### Model reference simulation target for nrhdlSIB1DemodulationCore is up to date. ### Model reference simulation target for nrhdlSSBDecodingCore is up to date. ### Model reference simulation target for nrhdlSSBDetectionCore is up to date. Build Summary 0 of 7 models built (7 models already up to date) Build duration: 0h 0m 1.9174s .................... MATLAB and Simulink grids relative MSE : -56.2924 dB Extracting CORESET0 candidates from the SIB1 grid. Decoding CORESET0 candidates using MATLAB reference. Decoding CORESET0 candidates using Simulink. Running nrhdlSIB1Recovery.slx ### Starting serial model reference simulation build. ### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date. ### Model reference simulation target for nrhdlDDCCore is up to date. ### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date. ### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date. ### Model reference simulation target for nrhdlSIB1DemodulationCore is up to date. ### Model reference simulation target for nrhdlSSBDecodingCore is up to date. ### Model reference simulation target for nrhdlSSBDetectionCore is up to date. Build Summary 0 of 7 models built (7 models already up to date) Build duration: 0h 0m 2.5059s .................... DCI from MATLAB: RIV: 528 TDDIndex: 0 VRBToPRBInterleaving: 0 ModCoding: 0 RV: 0 SIIndicator: 0 Reserved: 0 DCI from Simulink: RIV: 528 TDDIndex: 0 VRBToPRBInterleaving: 0 ModCoding: 0 RV: 0 SIIndicator: 0 Reserved: 0 DCI successfully decoded from Simulink grid with hardware acceleration Extracting LDPC codeword from the SIB1 grid. Decoding SIB1 using MATLAB reference. Decoding SIB1 using Simulink. Running nrhdlSIB1Recovery.slx ### Starting serial model reference simulation build. ### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date. ### Model reference simulation target for nrhdlDDCCore is up to date. ### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date. ### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date. ### Model reference simulation target for nrhdlSIB1DemodulationCore is up to date. ### Model reference simulation target for nrhdlSSBDecodingCore is up to date. ### Model reference simulation target for nrhdlSSBDetectionCore is up to date. Build Summary 0 of 7 models built (7 models already up to date) Build duration: 0h 0m 1.207s .......... SIB1 successfully decoded from Simulink grid with hardware acceleration SIB1 bits from MATLAB and Simulink match
HDL Code Generation and Implementation Results
To generate the HDL code for this example, you must have the HDL Coder™ product. Use the
makehdltb commands to generate HDL code and an HDL test bench for the
nrhdlSIB1Recovery/SIB1 Recovery subsystem. The resulting HDL code is synthesized for a Xilinx® Zynq® UltraScale+ RFSoC ZCU111 evaluation board. The table shows the post place and route resource utilization results. The design meets timing with a clock frequency of 245.76 MHz.
Resource Usage _______________ ______ Slice Registers 134191 Slice LUTs 93069 RAMB18 418 RAMB36 39 DSP48 216