DVB-S2 HDL PL Header Recovery Using Analog Devices AD9361/AD9364
This example shows how to deploy a DVB-S2 time, frequency, and phase synchronization and PL header recovery algorithm. This example uses DVB-S2 PL header recovery in a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform.
For a list of supported radio hardware platforms, see Hardware Support. Due to limited hardware resources, this example does not support Avnet ZedBoard and FMCOMMS2/3/4.
This example uses the PL header recovery implementation from the DVB-S2 HDL PL Header Recovery (Wireless HDL Toolbox) example to deploy a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform. This figure shows a conceptual overview of the example.
Digital Video Broadcasting Satellite Second Generation (DVB-S2) modems operate in C (4-8 GHz), Ku (12-18 GHz) and Ka (26-40 GHz) frequency bands. According to the DVB-S2 standard, the satellite transponder bandwidth ranges from 1 MHz to 72 MHz. The model in this example operates at a symbol rate of 25 Mbaud with a root raised cosine (RRC) filter roll-off factor of 0.35. For a MATLAB® implementation of end-to-end DVB-S2 receiver, see the End-to-End DVB-S2 Simulation with RF Impairments and Corrections (Satellite Communications Toolbox) example.
To work with the HW/SW co-design workflow, you must install and configure additional support packages and third-party tools. For more information, see Installation for Hardware-Software Co-Design.
Hardware Generation Model
This Simulink® model is a hardware generation model of the DVB-S2 transmit and physical layer (PL) header recovery algorithm for targeting software-defined radio (SDR) platforms. From this model, you can generate an HDL code for the programmable logic (PL) and generate a template software interface model using HDL Workflow Advisor. Using the template software interface model, you can generate an application that runs on the processing system (PS). This diagram shows a hardware subsystem and a sample test harness.
DVB-S2 PL Header Recovery HDL subsystem contains the functionality to be implemented on the PL. The ARM processor pulls the status signals information from the FPGA and displays the information on the host.
DVB-S2 PL Header Recovery HDL
DVB-S2 PL Header Recovery HDL subsystem is based on the DVB-S2 HDL PL Header Recovery (Wireless HDL Toolbox) example and adds additional functionality to integrate the model with the Zynq® hardware architecture.
Tx-LUT_Channel_Rx subsystem includes the
LUT Based Tx subsystem,
PL Header Recovery model reference, and
LUT Based Txsubsystem stores the DVB-S2 Tx transmitter waveform generated using the
PL Header Recoveryis a model reference implemented in the DVB-S2 HDL PL Header Recovery (Wireless HDL Toolbox) example.
Simulate Hardware Generation Model
Because the model contains several HDL-optimized blocks that use sample-based signals for simulation, running the model can take a while. After the simulation starts, double-click the Control Scope to see the Tx Filtered Spectrum, Rx In frequency offset time scope, Correlation Time Scope, Header and Data Constellation plots.
To enable the AWGN channel between the DVB-S2 Transmitter and Receiver, set enableNoise to
true. You can control the channel by using the channel impairments CFO, CPO, and EsNodB. When overAir is set to
true, the DVB-S2 signals are transmitted and received externally through the Tx and Rx antennas, where the channel impairments are added over the air in real time.
When the simulation behavior of the hardware subsystem is satisfactory, you can generate and integrate the HDL IP core with the SDR reference design and generate software for the ARM processor.
Generate IP Core
To generate the HDL IP core, right-click the
DVB-S2 PL Header Recovery HDL subsystem and select HDL Code > HDL Workflow Advisor.
Expand 1. Set Target and click 1.1. Set Target Device and Synthesis Tool. In the right pane, set Target workflow to
IP Core Generationand Target platform to
ZC706 and FMCOMMS2/3/4.
Click 1.2. Set Target Reference Design. In the right pane, set Reference design to
Receive and Transmit path. For this example, use the default settings in the Reference design parameters pane.
Click 1.3. Set Target Interface. In the right pane, under the Target platform interface table pane map the DUT signals to the interface signals available in the reference design. Because this example uses a single channel, configure the channel 1 connections and AXI register interfaces as shown in these figures.
Click 1.4. Set Target Frequency. In the right pane, set Target Frequency (MHz) to 61.44. For this example, use the default settings in the Set Target Frequency pane.
Click 2. Prepare Model for HDL Code Generation. In the right pane, click Run All. The app prepares the model for HDL code generation by performing design checks.
Click 3. HDL Code Generation. In the right pane, click Run All. The app generates HDL code for the IP core.
Next, continue to use the HDL Workflow Advisor to generate the software interface model and block library.
Generate Software Interface Model and Block Library
Expand 4. Embedded System Integration. This step integrates the newly generated IP core project into the Zynq SDR reference design, generates the corresponding bitstream, and loads the bitstream onto the board.
Click 4.1. Create Project. In the right pane, click Run This Task. The app creates a project for the embedded system tool.
Click 4.2. Generate Software Interface. In the right pane, click Run This Task. The app generates a software interface library and a template software interface model.
Software Interface Library
The library contains the AXI Interface block generated from the
DVB-S2 PL Header Recovery HDL subsystem. This block exposes only the AXI-lite control ports but not the data ports. The data ports are present on the transmitter and receiver blocks corresponding to your hardware selected in 1.1. Set Target Device and Synthesis Tool. The data ports of the transmitter and receiver blocks represent the streaming data interface between the FPGA user logic and ARM processor.
When using the library blocks in a downstream model, you must configure the parameters correctly for your application. Take into account that any updates to the
DVB-S2 PL Header Recovery HDL subsystem are automatically propagated to the library blocks in the downstream model when you run 4.2. Generate Software Interface again.
Template Software Interface Model
You can use the generated template software interface model as a starting point for full SW targeting, for example, in external mode simulation or full deployment. Because HDL Workflow Advisor overwrites the generated model each time you run 4.2. Generate Software Interface, consider saving the generated model under a unique name and develop your software algorithm in the newly saved model.
Generate and Load Bitstream
The last steps of the HDL Workflow Advisor generate a bitstream for the PL and download the bitstream onto the board.
Click 4.3. Build FPGA Bitstream. In the right pane, click Run This Task. The app generates a bitstream for the PL. You can execute this step in an external shell by selecting Run build process externally. This selection allows you to continue using MATLAB while building the FPGA image. After the basic project checks complete, the app marks this check with a green checkmark. However, you must wait until the external shell displays a successful bitstream build before moving on to the next step.
Click 4.4. Program Target Device. In the right pane, click Run This Task. The app downloads the bitstream onto the device. Before continuing with this step, call the
zynqfunction to ensure that MATLAB has the correct physical IP address for the radio hardware:
>> devzynq = zynq('linux','192.168.3.2','root','root','/tmp');
By default, the physical IP address of the radio hardware is 192.168.3.2. If you alter the radio hardware IP address during the hardware setup process, you must supply that address instead.
Alternatively, if you want to load the bitstream outside the HDL Workflow Advisor, create a SDR radio object by using sdrdev object and use the downloadImage function. The type of object you create depends on the Target platform setting in the 1.1. Set Target Device and Synthesis Tool pane.
If the selected radio platform is
ADI RF SOM,
ZC706 and FMCOMMS2/3/4, or
ZCU102 and FMCOMMS2/3/4, create an AD936x radio object.
>> radio = sdrdev('AD936x');
If the selected radio platform is
ZC706 and FMCOMMS5, create an FMCOMMS5 radio object.
>> radio = sdrdev('FMCOMMS5');
Download the bitstream using the radio object interfacing the selected radio device.
>> downloadImage(radio,'FPGAImage', ... 'hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top.bit') % Path to the generated bitstream
DVB-S2 Software Interface Model
The software interface model is based on the generated template software interface model.
The model is configured for the
Xilinx Zynq-7000 Based Board target. You can use this target for the
ADI RF SOM or
ZC706 and FMCOMMS2/3/4/5 radio platforms. For the
ZCU102 and FMCOMMS2/3/4 radio platform, you must reconfigure the model by selecting
Zynq UltraScale+ MPSoC ZCU102 IIO Radio in Model Settings (Ctrl+E) > Hardware Implementation > Hardware board or by double-clicking the provided Select Hardware Board Target.
Run Design on Zynq Board
You can run the DVBS2 software interface model in
Monitor & Tune mode. In this mode, you can control the configuration from the Simulink model. Alternatively, to deploy the design on the board disconnected from Simulink, click
Build Deploy & Start.
Host Interface Model
The ARM sends the DVBS2 Receiver output data and receiver status signals directly back to the host over the Ethernet link by using UDP Send blocks. The IP address of the UDP Send block must be the IP address of the host, by default, '192.168.3.1'. If you alter the IP address during the hardware setup process, you should apply that address instead.
This interface model, which runs on the host, illustrates how to receive data from the hardware platform and how to postprocess it.
When the host interface model successfully runs, the model displays the receiver status signals information from the FPGA.
To see the constellation plot, double-click the Control Scope. By default the software interface model sets modcod to 12 and overAir to
When the model is running on hardware, changing the overAir signal results in distorted constellation plot and status information. To switch between loopback modes, stop the simulation and toggle the overAir to select the desired mode. The following constellation plot is obtained when overAir is