Connect host computer and memory-mapped locations on your board or FPGA logic
Use these blocks to read and write memory-mapped locations and your SoC board.
|AXI4-Stream IIO Read (HOST)||Read DDR memory buffer from IP core device into simulation model|
|AXI4-Stream IIO Write (HOST)||Write arrays to DDR memory buffer of IP core device from simulation model|
|AXI4-Register IIO Read (HOST)||Read memory-mapped registers into simulation model|
|AXI4-Register IIO Write (HOST)||Write data to memory-mapped registers from a simulation model|
|Memory IIO Read||Read from a shared memory region into simulation model|
|Memory IIO Write||Write from simulation model to a shared memory region|