SDFM

The sigma delta filter module (SDFM) is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each input channel can receive an independent delta-sigma (ΔΣ) modulator bitstream. The bitstreams are processed by four individually-programmable digital decimation filters.

The filter set includes a fast comparator (secondary filter) for immediate digital threshold comparisons for over-current and under-current monitoring and a primary data filter.

Configure filter #

Configure the filter channel for the SDFM module. Each SDFM module has four filter channels.

Data pin assignment (SD#_D#)

Select the data input (GPIO pin) for each filter channel.

Clock pin assignment (SD#_C#)

Select the clock input (GPIO pin) for each filter channel.

For F2838x processor, the GPIO value that you set in the Clock pin assignment (SD#_C#) option of one filter channel can also be used in other filter channels.

Modulator clock mode

The input control unit is configured to receive the modulated data in following four modes:

Same as the modulator data rate (MOD_0) - The modulator clock runs with the modulator data rate. The modulator data is strobed at every rising edge of the modulator clock.
Half the modulator data rate (MOD_1) - The modulator clock runs with half of the modulator data rate. The modulator data is strobed at every edge of the modulator clock.
Manchester encoded (MOD_2) - The modulator clock is off and the modulator data is Manchester-encoded.
Twice the modulator data rate (MOD_3) - The modulator clock runs with double the modulator data rate. The modulator data is strobed at every other positive modulator clock edge.

Comparator filter type

The comparator filter is configured to one of the four filter types: SincFast, Sinc1, Sinc2, and Sinc3.

The comparator filter is a lowpass filter that converts the input bitstream into digital data by digital filtering and decimation.

Comparator over sampling ratio (COSR) [0-31]

The comparator OSR settings can be configured to the value ranging 0 to 31 and are independent of the data filter.

Effective number of bits (ENOB) of the comparator filter depends upon the comparator filter type, COSR, and the sigma-delta modulator frequency.

Comparator higher threshold (HLT#) [0-32767]

Comparator higher threshold (HLT) is used to detect the over-value condition when comparator data > = higher threshold register value (HLT) and generate an SDFM interrupt when interrupts are enabled.

HLT lies in the range 0 and 32767.

Comparator lower threshold (LLT#) [0-32767]

Comparator lower threshold (LLT) is used to detect the under-value condition when comparator data < = lower threshold register value (LLT) and generate an SDFM interrupt when interrupts are enabled.

LLT lies in the range 0 and 32767.

Comparator higher threshold (HLTZ) [0-32767]

Comparator higher threshold (HLTZ) is used to detect threshold crossing event condition when comparator data > = higher threshold register value (HLTZ) and does not generate an SDFM interrupt when interrupts are enabled.

The Comparator higher threshold (HLTZ) has a range between 0 and 32767.

Note

This parameter is available only for specific processors.

Data filter type

The data filter is configured to one of the four filter types: SincFast, Sinc1, Sinc2, and Sinc3.

The data filter is a lowpass filter that converts the input bitstream into digital data by digital filtering and decimation.

Data over sampling ratio (DOSR)

The data OSR settings can be configured from 0 to 255 and is independent of the comparator filter.

Effective number of bits (ENOB) of the data filter depend upon the data filter type, DOSR, and the sigma-delta modulator frequency.

Data filter FIFO depth

Each data filter has a 16-level deep 32-bit FIFO.

FIFO enables the data filter unit to reduce interrupt overhead.

Note

This parameter is available only for specific processors.

Enable data filter reset by ePWM

Enable to reset the data filter by external PWM compare output.

ePWM Module

Select the PWM module(PWM#SOCx) for synchronization.

This parameter is available only for specific processors.

Comparator event # (CEVT#) interrupt

Select the comparator event (CEVT#) interrupt.

This parameter is available only for specific processors.

Enable high level threshold crossing output (HLTZ)

Enable to detect an over-value condition.

HLTZ is used in conjunction with eCAP to measure the frequency or duty cycle of the threshold crossing events.

This parameter is available only for specific processors.

Enable modulator clock failure interrupt

Enable the interrupt for the modulator clock failure.

Enable data filter acknowledge interrupt

Enable the interrupt for new data acknowledgement.

When the primary filter is ready with new filter data, an acknowledgement (AFx) event is generated. For a few processors, data filter acknowledgement is from the FIFO ready data event.

Enable comparator lower threshold (LLT)

Will enable the SDFM interrupt to detect the under - value condition.

Enable comparator higher threshold (HLT)

Will enable the SDFM interrupt to detect the over- value condition.

Synchronize SD Data with PLLCLK

The data input to a filter can be synchronized with the PLL clock.

This parameter is available only for specific processors.

Synchronize SD Clock with PLLCLK

The clock input to a filter can be synchronized with the PLL clock.

This parameter is available only for specific processors.

SDFM

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