Main Content

F2837xD/F2838x/F2838x-M4 IPC Receive

Receive data from either core

expand all in page
  • Library:

  • Embedded Coder Support Package for Texas Instruments C2000 Processors / F2837xD

    Embedded Coder Support Package for Texas Instruments C2000 Processors / F2838x/ C28x

    Embedded Coder Support Package for Texas Instruments C2000 Processors / F2838x / M4

  • F2837xD/F2838x/F2838x-M4 IPC Receive block

Description

The IPC Receive block receives and outputs data sent from one Core to the other.

Core1 transmits data to its allocated memory (Core1-to-Core2 Message RAM) and receives data from the allocated memory of Core2 (Core2-to-Core1 Message RAM). Similarly Core2 transmits data to its allocated memory (Core2-to-Core1 Message RAM) and receives data from allocated memory of Core1 (Core1-to-Core2 Message RAM). For F2838xD, Core1/Core2 can be CPU1,CPU2 or ARM Cortex-M4 (CM) and for F2837xD, Core1/Core2 can be CPU1 or CPU2.

If Core1 and Core2 are both C28x core, then the data and channel structure between two cores are allocated in Message RAM and the data array is allocated in Global Shared RAM. In C28x core, by default all the channel structures are created in Message RAM.

However, if one of the core is ARM Cortex M4 (applicable only for F2838x), then the data array is allocated only using Message RAM as global shared RAM is not available between cores. In order to accommodate more data, only required channel structures are created in Message RAM. Hence if the channel number used for transmit block in one core does not match with the receive block in other core the data transmission will not occur.

A hardware interrupt block can be used along with the IPC Receive block for receiving data based on hardware interrupts.

  • C28x processor - Channels 0, 1, 2, and 3 are configured for hardware interrupts IPC0, IPC1, IPC2, and IPC3 respectively.

  • F2838x-M4 processor - Channels 0, 1, 2, 3, 4, 5, 6 and 7 are configured for hardware interrupts IPC0, IPC1, IPC2, IPC3, IPC4, IPC5, IPC6 and IPC7 respectively.

These hardware interrupts can be set in the hardware interrupt block using these parameters: CPU interrupt number 1 and PIE interrupt numbers 13, 14, 15, and 16 respectively.

Ports

Output

expand all

Data read from the other Core.

The status port outputs one of these values:

  • 0 — No errors

  • 1 — Data not available

  • 2 — Data type mismatch

  • 4 — Data length mismatch

  • 6 — Data type and Data length mismatch

Note

When no data is transmitted, the IPC receive block receives 0 of uint16 data type and data type mismatch status is displayed

Parameters

expand all

The source at which you want to receive data. The source selection is based on the processor you choose. For F2838x(C28x) processor, the source is either C28x (CPU1/CPU2) or ARM Cortex-M4 (CM). For F2838x-M4 ARM core processor, the source is CPU1 or CPU2.

The IPC Receive block mask displays the current source and the channel selected. For example, if the block displays C28x_Ch0, then the source is C28x (CPU1/CPU2) and channel is 0. Similarly if the IPC Receive block displays CM_Ch1, then the source is ARM Cortex-M4 (CM) and channel is 1.

Note

This parameter is only available for F2838x(C28x) and F2838x-M4 ARM core processors.

The channel at which you want to receive data. Each channel is a separate memory location in the shared memory.

Note

The transmitter and receiver have 32 channels each to transmit and receive data. For data transmission and reception, the transmitter and receiver must be set to the same channel number.

The type of data the block receives.

Vector data is stored in the global shared RAM, and the address of the data is stored in the MSGRAM.

The number of data units received at each sample time. If the data length is 1, the block interprets each incoming piece of data as a scalar value; if the data length is greater than 1, the block interprets each incoming piece of data as a vector with length equal to Data length. The maximum size for scalar and vector data is 32 bits.

When enabled, the Core waits until data is available from the other Core.

The time between data samples, measured in seconds. When you set this parameter to -1, Simulink® determines the best sample time for the block based on the block context within the model.

Model Examples

Inter-Processor Communication Using IPC Blocks

Inter-Processor Communication Using IPC Blocks

Use the IPC blocks to communicate between multiple cores of multi-core of Texas Instruments™ C2000™ processors using Simulink® models.

Open Example

Version History

Introduced in R2018a

See Also