Configure each signal value comparison
DC — Customized data capture object
Customized data capture
object, specified as an
hdlverifier.FPGADataReader System object.
name — Name of trigger component signal
Name of trigger component signal, specified as a character vector.
This name must match one of the signal names configured on creation of the input
DC. The signal must be configured as a possible
enable — Indication that signal is part of trigger condition
Indication that the signal is part of the trigger condition, specified as a numeric
false). To use this signal in the overall trigger condition, set
this value to
true). When you set this value to
false), the signal is not used for the
overall trigger condition.
value — Value to compare this signal to as part of the trigger condition
decimal | binary | hexadecimal |
'Rising edge' |
'Falling edge' |
The trigger condition comprises value comparisons of one or more signals. This input specifies the value to match for each signal.
For a multibit signal, specify a decimal, binary, or a hexadecimal value within the
range of the data type associated with the signal. While providing hexadecimal or binary
values, you can provide values with a combination of
x (don't care value) to enable bit masking. That means, while
comparing the values, the trigger condition ignores the place values with
x and provides the output.
To separate a group of bits for better readability, you can use
between bits. For example, you can represent a 32-bit binary value as
'0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX' and a 32-bit hexadecimal
For logical signals, specify a string that indicates the level or edge to match. For more information, see Triggers.
N — Trigger stage
integer from 1 to M
Trigger stage, specified as an integer from 1 to M, where
M is set by the Max
trigger stages parameter of the FPGA Data
Capture Component Generator tool. Use
N to set the trigger
Nth trigger stage. If you do not specify
N, by default, the function sets the trigger condition in trigger
Introduced in R2017a