CEI 56G-LR Compliance Kit
Characterize and validate the performance of a CEI 56G-LR channel design.
CEI 56G-LR is a common electrical interface (CEI) implementation agreement (IA) that supports 56 Gb/s over "Long Reach" (LR) chip-to-chip applications. The CEI-56G-LR Clause is part of the Common Electrical I/O 3.1 Implementation Agreement.
This kit is designed for analysis of a backplane channel design between module boards. The channel model is based on two module boards connected with two mated connectors with PCB trace.
This kit enables you to insert a channel design and characterize and validate its performance using the specification masks to determine if the channel has a high confidence of success. If the channel does not meet the compliance masks, COM, or BER estimates, further investigation or redesign, along with simulation, will need to be performed to determine possible changes to meet compliance.
Open CEI 56G-LR Kit
Open the CEI 56G-LR kit in the Serial Link Designer app using the
Project Name: CEI_56G_LR
Interface Name: CEI_56G_LR
Target Operating Frequency: From 36 Gb/s to 58 Gb/s (UI = 55.55 ps to 34.48 ps)
The CEI 56G-LR kit defines one schematic set. Schematic sheets are included for testing a CEI 56G-LR channel in the form of an S-parameter model. The model represents two mated connectors, a backplane and two plug-in cards. The masks defined for channel losses provided in this kit are given in the CEI 56G-LR specification .
Default – Schematic sheets focused on channel characterization and BER compliance.
For more information about the CEI 56G-LR channel compliance schematics, transfer net properties, and compliance rules, refer to the document CEI_56G_LR.pdf that is attached to this example as a supporting file.
 CEI-56G-LR –PAM4 Long Reach Interface. Contribution Number: OIF2014.380.03. oif2014.380.03-CEI-56G-LR-PAM-4.pdf. June 27, 2016.
 Common Electrical I/O (CEI) - Electrical and Jitter Interoperability. IA # OIF-CEI-03.1. February 18, 2014.