Low-Power DDR4 Architectural Kit
Implement a low-power DDR4 (LPDDR4) interface for pre-layout analysis or post-layout verification.
This LPDDR4 architectural signal integrity kit includes all the transfer nets, mask compliance checks, waveform processing levels and generic models for a LPDDR4 interface. This includes generic buffer models for the LPDDR4 controller and SDRAM, along with fully functional timing models and complete waveform processing levels. You can modify the kit to match your exact LPDDR4 implementation. Then, perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and timing margins.
Open LPDDR4 Kit
Open the LPDDR4 kit in the Parallel Link Designer app using the
For more information about the LPDDR4 architectural signal integrity kit, including block diagrams, system configurations, transfer nets and libraries, refer to the document LPDDR4.pdf that is attached to this example as a supporting file.