HDL Code Generation
Implement a Simulink® model or subsystem in hardware by generating HDL code and deploying that code on an Application-Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). These examples show how to generate HDL code from Simulink models. For more information on HDL code generation from Simulink models, see HDL Code Generation from Simulink (HDL Coder).
- FPGA-Based Beamforming in Simulink: Algorithm Design
This example shows the first half of a workflow to develop a beamformer in Simulink® suitable for implementation on hardware, such as a field programmable gate array (FPGA).
- FPGA-Based Beamforming in Simulink: Code Generation
This example shows the second half of a workflow to generate HDL code for a beamforming algorithm and verify that the generated code is functionally correct.
- Pulse-Doppler Radar Using Xilinx RFSoC Device (SoC Blockset Support Package for Xilinx Devices)
This example shows how to build, simulate, and deploy a pulse-Doppler radar system in Simulink® using an SoC Blockset® implementation targeted on the Xilinx Zynq® UltraScale+™ RFSoC evaluation kit.