You can access on-board memory locations from MATLAB, using the MATLAB AXI master
IP in your FPGA design, and the
aximaster object. The object
connects to the IP over a physical cable, and allows read and write commands to
slave memory locations from the MATLAB command line.
To use this feature, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package.
To access on-board memory locations from MATLAB®, you must include the MATLAB AXI master IP in your FPGA design. This IP connects to slave memory locations on the board. The IP also responds to read and write commands from the MATLAB command line, over JTAG, PCI Express, or Ethernet cable.
To set up the AXI master IP for access from MATLAB, follow these setup steps:
Include the MATLAB AXI master IP in your FPGA design. To add the path for the
IP files to your project, call the
In your FPGA project, specify which addresses the AXI master IP is allowed to access.
The AXI master IP supports AXI4 Lite, AXI4, and Altera® Avalon slave memory locations. The FPGA interconnect automatically converts AXI4 transactions to the protocol of each address.
Compile your FPGA project, including the MATLAB AXI master IP.
Connect your FPGA board to your host computer using a physical cable (JTAG, PCI Express, or Ethernet cable).
Program the FPGA with your compiled design.
Alternatively, you can perform these steps in the HDL Coder™ guided workflow by using a sample reference design, such as the one included in these examples: IP Core Generation Workflow Without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit (HDL Coder) or IP Core Generation Workflow without an Embedded ARM Processor: Xilinx Kintex-7 KC705 (HDL Coder).
Once the program is running on your FPGA board, you can create a MATLAB AXI master object,
aximaster. To access the slave
memory locations on the board, use the
writememory methods of this object.
When using JTAG as a physical connection to your board, you might have
additional IPs that use the same JTAG connection. Such IPs include FPGA data
capture, Altera SignalTap II, or Xilinx®
Vivado® Logic Analyzer cores. The MATLAB AXI master IP can coexist in your design with other IPs that use
the JTAG connection, however, only one of these applications can use the JTAG
cable at a time. Release the
to return the JTAG resource for use by other applications.
The most common conflicting use of the JTAG cable is to reprogram the FPGA. Stop any FPGA data capture or MATLAB AXI master JTAG connection before you can use the cable to program the FPGA.
The maximum data rate between host computer and FPGA is limited by the JTAG clock frequency. For Altera boards, the JTAG clock frequency is 12 MHz. or 24 MHz. For Xilinx boards, the JTAG clock frequency is 33 MHz. or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.