In a conventional VHDL® or Verilog® test bench, HDL code is used to describe the stimulus to a logic design and to check whether the design’s outputs match the specification. Many engineers, however, use MATLAB® and Simulink® to help with VHDL or Verilog test bench creation because the software provides productive and compact notation to describe algorithms, as well as visualization tools for examining algorithm behavior.
Engineers who use MATLAB and Simulink in this manner have a variety of choices for verifying that HDL realizations of algorithms are correct.
Verification Using HDL Cosimulation
Use a MATLAB or Simulink test bench in combination with an HDL simulator to verify the design under test (DUT). HDL Verifier™ automates this cosimulation process and performs communication and synchronization between MATLAB or Simulink and the HDL simulator. The MATLAB or Simulink test bench can compare the output values from the HDL simulator with expected values from a truth model and report miscompares.
Verification Using FPGA-in-the-Loop Simulation
Use a MATLAB or Simulink test bench with a DUT that has been programmed into a Xilinx®, Intel®, or Microsemi® FPGA development board with FPGA-in-the-loop simulation. HDL Verifier may be used in combination with FPGA vendor tools to compile the HDL, build a programming file, load it onto the development board, and perform communication between the MATLAB or Simulink session and the board. With FPGA-in-the-loop simulation, there is no need to generate a Verilog or VHDL test bench since MATLAB or Simulink serves this purpose.
Verification Using SystemVerilog DPI Test Bench
SystemVerilog, an extension of Verilog used for test bench development, is supported by all popular HDL simulators. Through the SystemVerilog Direct Programming Interface (DPI), you can integrate C/C++ code with simulators such as Synopsys® VCS®, Cadence® Incisive® or Xcelium™, and Mentor Graphics® ModelSim® or Questa®. Using HDL Verifier in combination with MATLAB Coder™ or Simulink Coder™, you can generate SystemVerilog DPI test benches for use in production verification environments.
HDL Verifier can generate SystemVerilog DPI test benches in two different forms:
- Component test bench: If you generate a C component from a Simulink subsystem for use as a DPI component, you can optionally generate a SystemVerilog test bench. The test bench verifies the generated DPI component against data vectors from your Simulink model.
- HDL code test bench: If you generate HDL code from a Simulink subsystem using HDL Coder, you can optionally generate a SystemVerilog test bench. This test bench compares the output of the HDL implementation against the results of the Simulink model.
Verification with the Universal Verification Methodology (UVM)
HDL Verifier can also generate UVM components directly from Simulink models. HDL Verifier generates SystemVerilog UVM sequence and scoreboard components from models of test benches. It also produces SystemVerilog files for a behavioral design under test (DUT). The behavioral DUT can then be replaced with hand-coded RTL or with RTL generated using HDL Coder.
The generated components can run as a complete UVM environment in Siemens EDA ModelSim® or Questa®, Cadence® Xcelium™, or Synopsys® VCS®.
