Stateflow while-logic dead loop
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Dingxin Wang
2024 年 3 月 28 日 6:51
編集済み: Fangjun Jiang
2024 年 3 月 29 日 19:13
I'am using stateflow to model a system.
With this logic i am expecting if the input is 1, the output should be 1. If the input is not 1, do nothing (it'a one-time logic, if the input is once not 1, the output will be none from then).
I used a step signal from 1 to 2 as an input. But the simulation can't proceed since its a dead loop at first time step. Why is that and how to solve this?
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Fangjun Jiang
2024 年 3 月 28 日 15:04
When input==1, you do have an infinite loop, right?
Connecting the feedback transition to the bottom junction would resolve it.
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Fangjun Jiang
2024 年 3 月 29 日 19:12
編集済み: Fangjun Jiang
2024 年 3 月 29 日 19:13
See this for Stateflow while-loop. You don't have anything to change the condition. Any time when input==1, it will fall to the infinite loop trap.
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