Demonstrates how to use the Embedded Coder Support Package for STMicroelectronics Discovery Boards to run a Simulink® model on an STMicroelectronics STM32F4-Discovery board or
Model a controller and implement it on a Xilinx® Zynq™-7000 All Programmable SoC target. This example is based on a ZedBoard using an Analog Devices motor control FMC board. Note that if you do
Communicate with the FPGA IP core on the Zynq hardware using AXI4®-Lite protocol. AXI4 (Advanced eXtensible Interface 4) is an ARM® standard.
Model a three band parametric equalizer algorithm and run it on the ARM® Cortex M based STMicroelectronics® STM32 Discovery boards.
Use the GPIO blocks in the STMicroelectronics STM32F4-Discovery library to control the push-button and the LED's on the STMicroelectronics STM32F4-Discovery board.
Use Embedded Coder Support Package to run a Simulink® model on MSP-EXP430G2 LaunchPad using Energia Toolchain.
Use the Embedded Coder Support Package for ARM Cortex-M Processors to run a Simulink model on an ARM Cortex-M3 emulator provided by QEMU.
Use Embedded Coder Support Package for STMicroelectronics Discovery Boards for code verification and validation using PIL and External mode.
Use code replacement libraries for ARM Cortex-M processors to generate optimized code for the STMicroelectronics STM32F4-Discovery board.
Configure the VxWorks® 7 operating system, generate code from a Simulink® model and run the executable on the Zynq hardware.
Model the ITU-T G.729 Voice Activity Detector (VAD) algorithm and run it on the ARM® Cortex-M based STMicroelectronics® STM32 Discovery boards.
Use Embedded Coder Support Package for BeagleBone Black Hardware to run a Simulink® models on BeagleBone Black hardware.
Generate code from a Simulink® model and run the executable on the Zynq hardware.
Send data using the UDP Ethernet protocol from a Simulink® model running on Zynq hardware to another model running on the host computer.
Use Embedded Coder™ Support Package for ARM Cortex-A Processors for real-time execution profiling of generated code.
Use the ALSA Audio Playback block from the BeagleBone Black block library to implement a parametric audio equalizer algorithm on BeagleBone Black hardware.
Model asynchronous scheduling using the Hardware Interrupt block for the STMicroelectronics STM32F4-Discovery board.
Use Embedded Coder Support Package for ARM Cortex-A Processors to run a Simulink® models on an ARM Cortex-A9 emulator.
Use Embedded Coder Support Package for BeagleBone Black Hardware to set the correct hardware pin mux configuration to run Simulink® models accessing the physical pins of the BeagleBone
Use the V4L2 Video Capture and the SDL Video Display blocks from the BeagleBone Black block library to implement an image inversion algorithm with a Simulink® model, and to run the model on
Use Embedded Coder™ Support Package for ARM Cortex-A® Processors for code verification and validation using PIL and External Mode.
Use Embedded Coder Support Package for ARM Cortex-M Processors for code verification and validation using PIL.
Use the function fixpt_look1_func_plot to find the maximum absolute error for the simple lookup table whose breakpoints are 0, 0.25, and 1. The corresponding Y data points of the lookup
Sample fixed-point implementations of a discrete lead filter and a discrete lag filter along with reference implementations in floating point.
This model shows how to exercise a custom C language S-function written to compute a fixed-point "product and sum" operation. To see the source code for the S-function, use the right-click
Find the approximation to an ideal function of y = sin(2*pi*x) over an input range [xmin,xmax] using a lookup table approach. Fixed-point applications often need to approximate a function
Implement a direct form filter in fixed point using fundamental building blocks such as Gain, Delay, and Sum.
Perform a floating-point and a fixed-point simulation of a fuel rate control system designed using Simulink® and Stateflow®. The controller leverages Simulink numeric types to switch
A custom C language S-function written to generate a constant value. This operation is available in Simulink® with the "Constant" block, which can be used for comparison with this
Use the FixPt To FixPt Inherited block. Because Simulink® propagates data types throughout a block diagram, fixed-point utility modeling can be templatized for multiple use scenarios.
Use derived range analysis to generate minimum and maximum range data that then can be used by the Fixed-Point Tool to propose fixed-point scaling.
Construct a fixed-point series cascade form filter using the fundamental building blocks of delay, sum, and gain.
Implement a parallel form filter in fixed point using fundamental building blocks such as Gain, Delay, and Sum.
Optimize fixed-point operations in generated code using minimum and maximum values that you specify in a model.
This model shows how sample implementations of filtered and unfiltered fixed-point derivative algorithms compare with their floating-point implementations.
This model shows how to propagate fixed-point data types in fixed-point S-Functions. It exercises a custom C language S-function written to enforce data types across multiple signals.
Use the Fixed-Point Advisor (FPA) to prepare a floating-point model or subsystem for conversion to fixed point. After preparation, use the Fixed-Point Tool to convert the floating-point
Use the Fixed-Point Tool, which is launched automatically upon opening the model. The tool is a graphical user interface (GUI) that automates common tasks of collecting min-max range data
A custom C language S-function written to perform an arithmetic shift. This operation is available in Simulink® with the "Shift Arithmetic" block, which can be used for comparison with this
Perform high precision calculations in the Interpolation Using Prelookup block using internal rules. The Interpolation block allows the data type for intermediate results to be set.
Control generation of multiword operations in generated code.
A comparison between various fixed-point integrator realizations and an equivalent floating point realization.
This model shows bit-true implementations of fixed-point direct type I and II filters with time-varying and time-invariant coefficients. These filters use the fundamental capabilities
This model shows how to convert signals between built-in and fixed-point data types and illustrates how fixed-point data types affect the representable precision and range. The
Control the generation of multiplication helper functions in the generated code.
Generate a cosimulation model in of HDL Coder and integrate the generated HDL code into an HDL Verifier™ workflow. Automation of cosimulation model generation enables seamless
Utilize RAM resources in your FPGA design using HDL Coder™.
Build an LTE compliant OFDM Modulator and Detector for implementation with HDL Coder™, and use LTE System Toolbox™ to verify the HDL implementation model.
Instantiate multiple top-level synchronous clock input ports in HDL Coder.
Use HDL Coder™ to check, generate and verify HDL for a fixed-point CORDIC model implementing sin and cos trigonometric functions using the MATLAB Function Block.
Use Xilinx® System Generator for DSP with HDL Coder™.
HDL support is provided for Gamma correction in Vision HDL Toolbox™. This example demonstrates the functionality of the pixel-stream Gamma Corrector block and compares the results with
Effectively use the MATLAB Function block to model commonly used hardware algorithms using HDL Coder™. An HDL design patterns library is used to show the features of MATLAB Coder supported
This model shows how to use HDL Coder™ to check, generate, and verify HDL code for a serial input serial output minimum resource HDL FFT model.
Use the Altera® DSP Builder Advanced Blockset with HDL Coder™.
Apply resource sharing in the presence of oversampling constraints.
Use distributed pipelining to optimize a design for speed in HDL Coder.
Balance delays in specific parts of a design, without balancing delays on the entire design.
How HDL Coder can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either
Demonstrates how to generate HDL code for a programmable FIR filter. You can program the filter to a desired response by loading the coefficients into internal registers using the host
HDL code generation support for the Viterbi Decoder block. It shows how to check, generate, and verify the HDL code you generate from a fixed-point Viterbi Decoder model. This example also
Optimize the QPSK transmitter modeled in the QPSK Transmitter and Receiver example for HDL code generation and hardware implementation.
Optimize the QPSK receiver modeled in QPSK Transmitter and Receiver example for HDL code generation and hardware implementation. The HDL-optimized model shows a QPSK receiver that
A hardware friendly model that receives beacon frames in an 802.11 wireless local area network (WLAN) as described in [ 1 ]. For more information refer to the IEEE 802.11 WLAN - Beacon Frame
Implement a 64-QAM transmitter and receiver for HDL code generation and hardware implementation. These models are based on the models HDL Optimized QPSK Transmitter and HDL Optimized QPSK
Demonstrates how to generate HDL code for a discrete FIR filter with multiple input data streams.
The RSim target was designed to let you run batch simulations at the fastest possible speed. Using variable-step or fixed-step solvers with RSim combined with the use of a tunable parameter
Optimize the generated code by using the memset function to clear the internal storage. When you select the model configuration parameter Use memset to initialize floats and doubles to 0.0,
Use Simulink Coder Support Package for NXP FRDM-KL25Z Board to control a servo motor connected to FRDM-TFC Shield.
Use Simulink Coder Support Package for NXP FRDM-KL25Z Board to run Simulink® model on a NXP FRDM-KL25Z board.
The Target for TI HERCULES RM48 MCUs package is dependent on a number of other Mathworks and TI software products. Before continuing, please make sure that all required prerequisites are
Use Simulink Coder Support Package for NXP FRDM-KL25Z for code verification and validation using External mode.
Use inline invariant signals to optimize the generated code. This optimization transforms symbolic names of invariant signals into constant values.
How the RSim -i option in Simulink® Coder™ lets you use a MAT-file as the input data source for Inport blocks for rapid simulations. The data in such a MAT-file can be presented in any of the
Select a target for a Simulink® model, generate C code for real-time simulation, and view generated files.
Generate code from a model and produce a Visual Studio Solution. For the base example, see rtwdemo_counter.
Place external code in generated code by using custom code blocks and model configuration parameters.
Optimize generated code by storing logical signals as Boolean data. When you select the model configuration parameter Implement logic signals as Boolean data (vs. double), blocks that
This function must be customized and then executed before the target support package for TI RM48 MCUs will run properly. Note: if you are viewing the abbreviated form of this help through the
This model shows an implementation of a second-order physical system called an ideal mass-spring-damper system. Components of the systems equation are listed as mass, stiffness, and
This model shows ASAP2 data export. ASAP2 is a data definition standard proposed by the Association for Standardization of Automation and Measuring Systems (ASAM).
Generate code for an air-fuel ratio control system designed with Simulink® and Stateflow®.
How the code generator combines for loops. The generated code uses for constructs to represent a variety of modeling patterns, such as a matrix signal or Iterator blocks. Using data
Integrate legacy C functions that pass their inputs and outputs by using parameters of a fixed-point data type with the Legacy Code Tool.
Identify required files and interfaces for calling generated code in an external build process.
Optimize the amount of memory that the code generator allocates for time counters. The example optimizes the memory that stores elapsed time, the interval of time between two events.
Run a processor in the loop (PIL) Simulation using the Target for TI HERCULES™ RM48 MCUs package.
When you use a MATLAB® structure to specify initialization values for the signal elements in a bus, you can create a tunable global structure in the generated code.
Stateflow and MATLAB Coder can fully define their data definitions, or they can inherit them from Simulink. Data definition capabilities include:
Open up the "Controller" subsystem. Notice that this model uses a Triggered Stateflow® Chart to do the "Enable" and "Setpoint" calculation. It uses a discrete PID Controller to compute the
This model shows the code generated for a Stateflow chart which uses absolute time temporal logic. Simulate the model. Click on the scope to observe the "pulse" output.
Open up the "Controller" subsystem. Open the Stateflow® chart named "Control" chart inside it. This chart implements the control logic for starting and stopping the conveyer belt motor
This model shows how to integrate user defined function blocks, data types and global variables into generated structured text
This model shows how tunable parameters map to Structured Text by specifying them as Simulink.Parameter objects in MATLAB base workspace.
This model shows the code generated for a Feedforward PID Controller implemented using Simulink library blocks.
In this model, the model solver is set to variable-step continuous (ode45); the sample time of the controller subsystem is set to 0.05. To set the controller sample time, right click on the
This model shows the code generated for a Stateflow chart.
This model shows the code generated for a MATLAB block implementing tank valve control logic.
This model shows the code generated for a simple subsystem without internal state.
This model shows how to map tunable parameters from the Simulink® model to the generated Structured Text code.
This model shows the workflow for simulating and generating Structured Text code for Motion Instructions. For more information on this workflow, please refer to the "Simulation and Code
This model shows the code generated for a simple subsystem consisting of a few basic Simulink blocks.
Open the subsystem at the top level named 'Subsystem'. Simulate the model and observe the fixed point types displayed on the signals.
This introductory model shows the code generated for a hierarchical subsystem consisting of other Simulink subsystems.
This introductory model shows the code generated for a hierarchical subsystem consisting of other Simulink subsystems.
This model shows the code generated for a simple subsystem using multirate.
This model shows the code generated for a reusable subsystem consisting of a few basic Simulink blocks.