HDL Coder Workshop

Seminar Overview

Following the conversation with your MathWorks account manager, you are now invited to confirm your attendance at our Simulink HDL Coder Workshop.

HDL code generation and verification tools from MathWorks extend the Model-Based Design methodology.  MathWorks provides you with a single integrated tool environment for the implementation of algorithms in digital hardware. Abstract simulation models are incrementally refined to reflect the impact of hardware implementation, and HDL code generation then automates the RTL production for implementation in an FPGA or ASIC. This results in an acceleration of the complete development process.

This workshop provides hands-on experience to examine how:

  • Filter Design HDL Coder can be used to generate bit-true, cycle-accurate, synthesizable Verilog and VHDL code using different implementation architectures. The generated HDL code can be verified through an automatically generated co-simulation model.
  • Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Stateflow charts, and Embedded MATLAB code. The automatically generated HDL is technically and contractually target independent.
  • Using self worked examples, the workshop will provide a basic understanding of automatic code generation for FPGAs and ASICs and test bench verification in co-simulation with the popular HDL verification products and FPGA hardware.

The workshop is not publicised and attendance is by invitation only. Spaces are very limited and although there is no charge to you please let us know if after registering you are unable to attend so that we can offer your place to another.